Results 121 to 130 of about 341 (156)

In Situ Fault Detection of Wafer Warpage in Microlithography

IEEE Transactions on Semiconductor Manufacturing, 2004
Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability and linewidth control in various processing steps. We proposed in this paper an in situ fault detection technique for wafer warpage in microlithography. Early detection will minimize cost and processing time. Based on first principle thermal
W.K. Ho, A. Tay, Y. Zhou, K. Yang
openaire   +1 more source

Wafer warpage control by epoxy molding compounds for wafer level package

2018 China Semiconductor Technology International Conference (CSTIC), 2018
The recent interest of Fan-out wafer level packaging technology (FOWLP) comes from such benefits, thin package, board fan-out capability, high I/O, good thermal resistance, and electrical performance. However, its application is limited due to the difficulty in the warpage control of FOWLP.
Kihyeok Kwon, Joo Young Chung, Donghwan Lee, Sang Kyun Kim   +3 more
openaire   +1 more source

Wave Front Phase Imaging of Wafer Warpage

2018 International Wafer Level Packaging Conference (IWLPC), 2018
We present a new wafer metrology technique called Wave Front Phase Imaging (WFPI) for high speed measurement of wafer warpage and nanotopography. This is accomplished by acquiring a single image snapshot using that provides depth data for every single pixel. The number of topography data points for the entire wafer will be proportional to the number of
Juan Trujillo, Jose Manuel Ramos Rodrigues   +1 more
openaire   +2 more sources

Process emulation for predicting die shift and wafer warpage in wafer reconstitution

2017 18th International Conference on Electronic Packaging Technology (ICEPT), 2017
Wafer reconstitution is a vital process for serving as a buffer to decouple the processing developments between IC fabrication and electronics packaging. By this approach, the IC packaging is then independent from the chip processing. However, such a process brings numerous mechanical loadings during molding and curing phases.
C.-Y. Yang, Y.-C. Liu, K.-S. Chen, T.-S. Yang, Y.-C. Wang, S.-S. Lee   +5 more
openaire   +1 more source

The analysis of warpage in wafer-level compression molding

Microsystem Technologies, 2015
Advanced 3D MEMS packaging technologies involving the encapsulation of devices at wafer-level are being developed in order to achieve further minimization and cost reduction of consumer electronic devices. Compression molding using epoxy molding compounds is one technique being considered for wafer-level encapsulation.
Russell Farrugia, Ivan Grech, Owen Casha, Edward Gatt, Joseph Micallef, Ivan Ellul, Roseanne Duca, Ingram Borg   +7 more
openaire   +1 more source

Full-field wafer warpage measurement technique

SPIE Proceedings, 2017
An innovative moire technique for full-field wafer warpage measurement is proposed in this study. The wafer warpage measurement technique is developed based on moire method, Talbot effect, scanning profiling method, stroboscopic, instantaneous phase-shift method, as well as four-step phase shift method, high resolution, high stability and full-field ...
H. L. Hsieh, J. Y. Lee, Y. G. Huang, A. J. Liang, B. Y. Sun   +4 more
openaire   +1 more source

A Predictive Model of Wafer-to-Die Warpage Simulation

2023 22nd IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2023
Quang Nguyen, Christopher Glancey, Wei Chang Wong, Raj Bansal   +3 more
exaly   +2 more sources

IN-SITU FAULT DETECTION OF WAFER WARPAGE IN LITHOGRAPHY

IFAC Proceedings Volumes, 2005
Abstract Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability and linewidth control in various processing steps. We proposed in this paper an in-situ fault detection technique for wafer warpage in lithography. Early detection will minimize cost and processing time.
Arthur TAY, HO Weng Khuen, Christopher YAP, Chen WEI, Kuen-Yu TSAI   +4 more
openaire   +1 more source

Process Induced Wafer Warpage Optimization for Multi-chip Integration on Wafer Level Molded Wafer

2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019
In this paper, the demonstration of test vehicle by two kinds of process flows noted as "C4 first" and "C4 last", which integrate chips on mold-based, Cu via wafer with glass carriers, are presented. Their warpage behavior during wafer-form integration will be experimentally and numerically evaluated, and also compared with wafer warpages of 2.5D ...
Chen-Yu Huang, Daniel Ng, Hung-Ho Lee, Vito Lin, Chang-Fu Lin, C. Key Chung   +5 more
openaire   +1 more source

Wafer warpage, crystal bending and interface properties of 4H-SiC epi-wafers

Diamond and Related Materials, 1997
Abstract The relationship between the warpage of 4H-SiC CVD grown epi-wafers with crystal bending and substrate properties is investigated. The wafer surface preparation before and after epitaxy is found to affect both long range properties such as the wafer flatness and to some extent local properties such as the epi-substrate interface.
Ellison A, Radamson H, Tuominen M, Milita S, Hallin C, Henry A, Kordina O, Tuomi T, Yakimova R, Madar R, Janzen E   +10 more
openaire   +1 more source