Results 111 to 120 of about 341 (156)

Low-Warpage Encapsulants for Wafer Level Packaging

Wafer-Level Packaging Symposium, 2020
ABSTRACT Wafer level encapsulation has become increasingly important to build up components for mobile and high-performance computing applications. Ranging from system-in-package and antenna modules to high band-width memory device, many of those wafer-level applications demand new features from encapsulant materials.
Jay Chao, Rong Zhang, David Grimes, Kail Shim, Tu Do, Yijia Ma, Ramachandran K. Trichur, Roozbeh Sheikh   +7 more
openaire   +2 more sources

Study of wafer warpage reduction by dicing street

Japanese Journal of Applied Physics, 2022
Abstract Wafer warpage occurs during the fabrication process, which induces many issues such as wafer handling, lithography alignment, device reliability. The efficiency of dicing street on wafer warpage reduction is investigated by varying the width, depth, and pitch of dicing.
Wei Feng, Haruo Shimamoto, Tsuyoshi Kawagoe, Ichirou Honma, Masato Yamasaki, Fumitake Okutsu, Takatoshi Masuda, Katsuya Kikuchi   +7 more
openaire   +1 more source

Warpage Analysis of Wafers With Film Coating

Packaging, Reliability and Manufacturing Issues Associated With Electronic and Photonic Products, 2001
Abstract Wafer-level packaging (WLP) is one of the trends of electronic packaging in the 21st century. Since 1994, many companies have released WLP licenses. One of the common concerns among these various approaches is wafer warpage. Warpage of wafer tends to introduces crack or delamination during dicing and low temperature storage ...
Hai Ding, I. Charles Ume, Cheng Zhang
openaire   +1 more source

Wafer level warpage characterization of 3D interconnect processing wafers

SPIE Proceedings, 2012
We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of
Po-Yi Chang, Yi-Sha Ku
openaire   +1 more source

Ashing Process on Warpage Wafer with Low Damage

2021 China Semiconductor Technology International Conference (CSTIC), 2021
To improve the surface quality of polyimide (PI) or photoresist (PR) ashing/striping on warpage wafer, the issues of arcing, peeling and damage should be overcome. In this work, we demonstrate a time-multiplexed alternating ashing (TMAA) process for 12-inch warpage wafer. The TMAA process can reduce the risk of arcing and peeling with higher uniformity.
Zihan Dong, Yuanwei Lin, Yuwei Kong
openaire   +1 more source

Wafer level warpage modeling methodology and characterization of TSV wafers

2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011
Through-silicon-via (TSV) approach has been widely investigated recently for three-dimensional (3D) electronic packaging integration. TSV wafer warpage is one of the most challenges for successfully subsequent processes. In this work, wafer level warpage modeling methodology has been developed by finite element analysis (FEA) method using equivalent ...
F. X. Che, H. Y. Li, Xiaowu Zhang, S. Gao, K. H. Teo   +4 more
openaire   +1 more source

Assessment of thinned Si wafer warpage in 3D stacked wafers

2009 11th Electronics Packaging Technology Conference, 2009
3D (three-dimensional) wafer stacking technology has been developed extensively recently. Among many technical challenges in 3D stacked wafers the wafer warpage is one of the important processing issues to be resolved because the wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical ...
Youngrae Kim, Sung-Geun Kang, Eun-kyung Kim   +2 more
openaire   +1 more source

Detection of wafer warpages during thermal processing in microlithography

ICARCV 2004 8th Control, Automation, Robotics and Vision Conference, 2004., 2005
Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability and linewidth control in various processing steps. We proposed in this paper an in situ fault detection technique for wafer warpage in microlithography. Early detection would minimize cost and processing time.
Weng Khuen Ho, Arthur Tay, Ying Zhou, Kai Yang, Ni Hu   +4 more
openaire   +1 more source

Warpage simulation for the reconstituted wafer used in fan-out wafer level packaging

Microelectronics Reliability, 2018
Abstract Fan-out packaging technology involves processing redistribution interconnects on reconstituted wafer, which takes the form of an array of silicon dies embedded in epoxy molding compound (EMC). Yields of the redistribution interconnect processes are significantly affected by the warpage of the reconstituted wafer.
Tz-Cheng Chiu, En-Yu Yeh
openaire   +1 more source

Warpage Characterization of Molded Wafer for Fan-Out Wafer-Level Packaging

Journal of Electronic Packaging, 2019
Abstract This study presents a comprehensive assessment of the process-induced warpage of molded wafer for chip-first, face-down fan-out wafer-level packaging (FOWLP) during the fan-out fabrication process. A process-dependent simulation methodology is introduced, which integrates nonlinear finite element (FE) analysis and element death ...
Hsien-Chie Cheng, Yan-Cheng Liu
openaire   +1 more source