System calibration method for Silicon wafer warpage measurement
ABSTRACT As a result of a mismatch of the residual stress between both sides of the silicon wafer, which warps and distorts during the patterning process. The accuracy of the warpage measurement is related to the calibration. A CCD camera was used for the calibration.
openaire +2 more sources
Design and Implementation of High-Capacity DDR3 Micro-Module Based on 3D TSV Advanced Packaging. [PDF]
Ji H +5 more
europepmc +1 more source
A Review of Polymer Dielectrics for Redistribution Layers in Interposers and Package Substrates. [PDF]
Nimbalkar P +4 more
europepmc +1 more source
Wafer-Level Transfer of GaN-on-Si Light-Emitting Devices via SiO<sub>2</sub>-SiO<sub>2</sub> Direct Bonding: Strain Evolution and Optoelectronic Performance. [PDF]
Zhang S, Zhang S, Fan Q, Ni X, Gu X.
europepmc +1 more source
Fabrication of Polyimide/Aluminum Nitride Composites and Wafer Channel Filling via Direct Ink Writing. [PDF]
Xiao J +5 more
europepmc +1 more source
Die shift prediction of fan out panel level packages considering both warpage and flow induced mechanisms with temperature dependent properties. [PDF]
Sung YC +7 more
europepmc +1 more source
CTE match of copper foil and build-up film/core board in FCBGA substrate reduces warpage. [PDF]
Wong W, Chiang ST, Huang JCS, Zhou XD.
europepmc +1 more source
Underfill: A Review of Reliability Improvement Methods in Electronics Production. [PDF]
Plachý Z +3 more
europepmc +1 more source
Residual stress modulation as a pathway to reliable multilevel 3D NAND flash storage. [PDF]
Zhou R, Kim IJ, Park S, Kwon H, Lee JS.
europepmc +1 more source
T-ray Wavelength Decoupled Imaging and Profile Mapping of a Whole Wafer for Die Sorting and Analysis. [PDF]
Rahman A.
europepmc +1 more source

