A Novel Capacitorless 1T DRAM with Embedded Oxide Layer [PDF]
Micromachines, 2022 A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of ...
Dongxue Zhao +5 more
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Circuit Optimization Method to Reduce Disturbances in Poly-Si 1T-DRAM [PDF]
Micromachines, 2021 A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM).
Yejin Ha +3 more
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Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM [PDF]
Micromachines, 2020 A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM).
Songyi Yoo, Wookyung Sun, Hyungsoon Shin
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Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM [PDF]
Micromachines, 2020 Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM).
Hyeonjeong Kim +5 more
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Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors [PDF]
Micromachines, 2023 Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices.
Juhee Jeon, Kyoungah Cho, Sangsig Kim
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The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET [PDF]
Nanoscale Research Letters, 2017 The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM).
Wei Li +4 more
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Dopingless 1T DRAM: Proposal, Design, and Analysis [PDF]
IEEE Access, 2019 In this paper, we have proposed a dopingless 1T DRAM (DL-DRAM) that utilizes the charge plasma concept. The proposed device employs a misaligned double-gate architecture to store holes and differentiates between the two logic states.
Akhil James, Sneh Saurabh
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A Novel One-Transistor Dynamic Random-Access Memory (1T DRAM) Featuring Partially Inserted Wide-Bandgap Double Barriers for High-Temperature Applications [PDF]
Micromachines, 2018 These days, the demand on electronic systems operating at high temperature is increasing owing to bursting interest in applications adaptable to harsh environments on earth, as well as in the unpaved spaces in the universe.
Myeongsun Kim +5 more
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Simulation Perspectives of Sub-1V Single-Supply Z2-FET 1T-DRAM Cells for Low-Power [PDF]
IEEE Access, 2019 With the upcoming Internet of Things (IoT), low-power devices are becoming mainstream these days. The need for memory elements able to operate at reduced biasing conditions is therefore of utmost importance.
Carlos Navarro +6 more
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LOW POWER AND IMPROVED SPEED 1T DRAM USING DYNAMIC LOGIC [PDF]
Journal of Engineering Science and Technology, 2018 The new trend of the DRAM design is to characterize by its reliability, delay, low power dissipation, and area. This paper dealt with the design of 1-bit DRAM and efficient implementation of a sense amplifier.
T. NIRMALRAJ +2 more
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