Results 11 to 20 of about 26,331 (111)
The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET
Nanoscale Research Letters, 2017 The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM).
Wei Li +4 more
doaj +2 more sources
Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances
IEEE Access, 2021 In this work, a capacitorless one-transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) metal–oxide–semiconductor field-effect transistor was designed and analyzed through a technology computer-aided
Sang Ho Lee +8 more
doaj +1 more source
Memories - Materials, Devices, Circuits and Systems, 2023 TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust ...
Koji Sakui +6 more
doaj +1 more source
, 2022 학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2022.2,[ii, 47 p. :]As DRAM scaling continues, development becomes more difficult due to insufficient amount of capacitor charge and increased process difficulty.
Lee, Jung-Hak
core +1 more source
Memory Operation of Z²-FET Without Selector at High Temperature
IEEE Journal of the Electron Devices Society, 2021 The electrical performance of Z2-FET and memory operations of matrix are demonstrated at high temperatures up to 125 °C. The sharp subthreshold slope is maintained and the reliable operation is ensured within the memory window of 229 mV even ...
S. Kwon +5 more
doaj +1 more source
Raised Body Doping-Less 1T-DRAM With Source/Drain Schottky Contact
IEEE Journal of the Electron Devices Society, 2019 In this paper, we propose a novel structure of doping-less 1T-DRAM with raised body and Schottky contact to source/drain regions which uses thermionic emission to generate electrons and holes.
Jyi-Tsong Lin +5 more
doaj +1 more source
Analysis of operation characteristics of junctionless poly-Si 1T-DRAM in accumulation mode
, 2021 Capacitorless DRAM (1T-DRAM) is considered to be a promising candidate to replace conventional 1T-1C DRAM which is facing a scaling limit. 1T-DRAM with a poly-Si body has attracted much attention specifically for its simple SOI fabrication and stackable ...
선우경, 신형순
core +1 more source
Dopingless 1T DRAM: Proposal, Design, and Analysis
IEEE Access, 2019 In this paper, we have proposed a dopingless 1T DRAM (DL-DRAM) that utilizes the charge plasma concept. The proposed device employs a misaligned double-gate architecture to store holes and differentiates between the two logic states.
Akhil James, Sneh Saurabh
doaj +1 more source
A2RAM nanowires fabrication and characterization for 1T-DRAM applications
, 2021 International audienceA2RAM devices are fabricated using an adaptation of Si-Nanowire process flow. They include a Si-SiGe heterostructure to improve memory performance.
P. Besson +23 more
core +1 more source
A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage
IEEE Journal of the Electron Devices Society, 2017 We experimentally demonstrate a new type of silicon-based capacitorless one-transistor dynamic random access memory (1T-DRAM) with an electron-bridge channel. The fabrication steps are fully compatible with modern CMOS technology.
Jyi-Tsong Lin +5 more
doaj +1 more source