Results 1 to 10 of about 108 (78)
A Novel Capacitorless 1T DRAM with Embedded Oxide Layer
A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of ...
Zhiliang Xia, Tao Yang, Zongliang Huo
exaly +3 more sources
An Output-Capacitorless Low-Dropout Regulator with Slew-Rate Enhancement
A novel output-capacitorless low-dropout regulator (OCL-LDO) with an embedded slew-rate-enhancement (SRE) circuit is presented in this paper. The SRE circuit adopts a transient current-boost strategy to improve the slew rate at the gate of the power ...
Sannian Song +2 more
exaly +3 more sources
Gateless and Capacitorless Germanium Biristor with a Vertical Pillar Structure
For the first time, a novel germanium (Ge) bi-stable resistor (biristor) with a vertical pillar structure was implemented on a bulk substrate. The basic structure of the Ge pillar-typed biristor is a p-n-p bipolar junction transistor (BJT) with an open ...
Yang-Kyu Choi, Gb Lee, Hagyoul Bae
exaly +3 more sources
Digitally Programmable Partially Active-R Sinusoidal Oscillators
New, simple sinusoidal oscillator circuits are proposed. Each circuit uses an internally compensated operational amplifier, a resistor, and a capacitor.
Muhammad Taher Abuelma'atti +3 more
doaj +2 more sources
Capacitorless two‐transistor‐zero‐capacitor (2T0C) dynamic random‐access memories (DRAMs) offer scalability, simplified processing, and design flexibility by eliminating storage capacitors. We propose 2T0C DRAMs using aluminum‐doped indium tin zinc oxide
Chahwan Yang +3 more
doaj +2 more sources
In electrolytic capacitorless permanent magnet synchronous motor (PMSM) drives, the DC-link voltage will fluctuate in a wide range due to the use of slim film capacitor. When the flux-weakening current is lower than −ψf/Ld during the high speed operation,
Junya Huo +6 more
doaj +1 more source
SOI nanodevices and materials for CMOS ULSI
A review of recently explored new effects in SOI nanodevices and materials is given. Recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI are ...
Francis Balestra
doaj +1 more source
Si1−xGex nanowire based metal‐semiconductor‐metal Schottky biristor: Design and sensitivity analysis
Abstract The incorporation of Si1−xGex nanowire based metal‐semiconductor‐metal (MSM) Schottky biristor allows the conceptualization and realization of low latch‐up and latch‐down voltages with retained latching window. With the aim of investigating the device governing physics and device performance, mathematical simulation is carried out using ...
Shaleen Nr, Sangeeta Singh, Pankaj Kumar
wiley +1 more source
Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances
In this work, a capacitorless one-transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) metal–oxide–semiconductor field-effect transistor was designed and analyzed through a technology computer-aided
Sang Ho Lee +8 more
doaj +1 more source
Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon nanotube structure with a grain boundary (GB) is designed and analyzed using technology computer-aided design (TCAD) simulation.
Jin Park +11 more
doaj +1 more source

