Results 101 to 110 of about 26,331 (111)
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Ramulator: A Fast and Extensible DRAM Simulator
IEEE Computer Architecture Letters, 2016Onur Mutlu, Yoongu Kim
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Design-Induced Latency Variation in Modern DRAM Chips
Proceedings of the ACM on Measurement and Analysis of Computing Systems, 2017Onur Mutlu +2 more
exaly
Applying PSO-based BPN for predicting the yield rate of DRAM modules produced using defective ICs
International Journal of Advanced Manufacturing Technology, 2009Zne-Jung Lee +2 more
exaly
DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing
IEEE Transactions on Computers, 2016Lee-Sup Kim +2 more
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Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture
Transactions on Architecture and Code OptimizationAtaberk Olgun +2 more
exaly

