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A High-yield Process Design for Self-aligned SOI MOSFET with Block Oxide and Its Characterization and Application for 1T-DRAM

, 2009
In this paper, we propose a high-yield self-aligned process to form a silicon-on-insulator MOSFET with block oxide for 1T DRAM use. The new process can overcome the problem of the previous one [1], which cannot be used for a thin BOX devices.
Tseng, Yi-ming
core  

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An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process

IEEE Access, 2021
Ki Chul, Sungho Kang, Kyomin Sohn
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DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator

IEEE Computer Architecture Letters, 2020
Zhiyuan Yang, Shang Li, Bruce Jacob
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DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023
Ataberk Olgun, Lois Orosa, Onur Mutlu
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WinDRAM: Weak rows as in‐DRAM cache

Concurrency Computation Practice and Experience, 2022
Shirshendu Das
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Understanding Reduced-Voltage Operation in Modern DRAM Devices

Proceedings of the ACM on Measurement and Analysis of Computing Systems, 2017
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A survey of techniques for improving error-resilience of DRAM

Journal of Systems Architecture, 2018
Maruthi S Inukonda, Sparsh Mittal
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What Your DRAM Power Models Are Not Telling You

Proceedings of the ACM on Measurement and Analysis of Computing Systems, 2018
Niladrish Chatterjee, Donghyuk Lee, Kevin K Chang   +2 more
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p73 regulates DRAM-independent autophagy that does not contribute to programmed cell death

Cell Death and Differentiation, 2007
Kevin M Ryan
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DRAM Refresh Mechanisms, Penalties, and Trade-Offs

IEEE Transactions on Computers, 2016
Bruce Jacob
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