Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure [PDF]
Nanomaterials, 2022 In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using ...
Hee Dae An +11 more
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Memory Operation of Z²-FET Without Selector at High Temperature [PDF]
IEEE Journal of the Electron Devices Society, 2021 The electrical performance of Z2-FET and memory operations of matrix are demonstrated at high temperatures up to 125 °C. The sharp subthreshold slope is maintained and the reliable operation is ensured within the memory window of 229 mV even ...
S. Kwon +5 more
doaj +4 more sources
InGaAs Capacitor-Less DRAM Cells TCAD Demonstration [PDF]
IEEE Journal of the Electron Devices Society, 2018 2D numerical TCAD simulations are used to infer the behavior of III-V capacitor-less dynamic RAM (DRAM) cells. In particular, indium gallium arsenide on insulator technology is selected to verify the viability of III-V meta-stable-dip RAM cells. The cell
Carlos Navarro +7 more
doaj +5 more sources
Ferroelectric-Metal Field-Effect Transistor With Recessed Channel for 1T-DRAM Application [PDF]
IEEE Journal of the Electron Devices Society, 2022 The ferroelectric-metal field-effect transistor with recessed channel (RC-FeMFET) is proposed for one transistor dynamic random-access memory (1T-DRAM). Through technology computer-aided design (TCAD) simulations, the effects of inter-metal insertion on ...
Kitae Lee +4 more
doaj +2 more sources
Novel three-dimensional stacked capacitorless DRAM architecture using partially etched nanosheets for high-density memory applications [PDF]
Discover NanoThis study presents a novel three-dimensional stacked capacitorless dynamic random access memory (1T-DRAM) architecture, designed using a partially etched nanosheet (PE NS) to overcome the scaling limitations of traditional DRAM designs.
Min Seok Kim +9 more
doaj +2 more sources
Reliability Study of Thin-Oxide Zero-Ionization, Zero-Swing FET 1T-DRAM Memory Cell [PDF]
, 2019 The experimental time-dependent dielectric breakdown and ON voltage reliability of advanced FD-SOI Z2-FET memory cells are characterized for the first time.
Santiago Navarro +6 more
openalex +5 more sources
On the Low-Frequency Noise Characterization of Z2-FET Devices [PDF]
IEEE Access, 2019 This paper addresses the low-frequency noise characterization of Z2-FET structures. These double-gated p-i-n diode devices have been fabricated at STMicroelectronics in an ultrathin body and box (UTBB) 28-nm FDSOI technology and designed to operate as 1T-
Carlos Marquez +8 more
doaj +5 more sources
Multi-Level Cell Structure for Capacitor-Less 1T DRAM With SiGe-Based Separated Data Storing Regions
IEEE AccessOne-transistor dynamic random-access memory (1T DRAM) offers significant advantages in fabrication process and scalability over the traditional one-transistor one-capacitor (1T-1C) DRAM due to its simplified structure that eliminates the need for ...
Eungi Hwang +3 more
doaj +2 more sources
A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage
IEEE Journal of the Electron Devices Society, 2017 We experimentally demonstrate a new type of silicon-based capacitorless one-transistor dynamic random access memory (1T-DRAM) with an electron-bridge channel. The fabrication steps are fully compatible with modern CMOS technology.
Jyi-Tsong Lin +5 more
doaj +2 more sources
Raised Body Doping-Less 1T-DRAM With Source/Drain Schottky Contact [PDF]
IEEE Journal of the Electron Devices Society, 2019 In this paper, we propose a novel structure of doping-less 1T-DRAM with raised body and Schottky contact to source/drain regions which uses thermionic emission to generate electrons and holes.
Jyi-Tsong Lin +5 more
doaj +2 more sources