Results 21 to 30 of about 930 (217)
Optimization Considerations for Short Channel Poly-Si 1T-DRAM [PDF]
Electronics, 2020 Capacitorless one-transistor dynamic random-access memory cells that use a polysilicon body (poly-Si 1T-DRAM) have been studied to overcome the scaling issues of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Generally, when the gate length of a silicon-on-insulator (SOI) structure metal-oxide-silicon field-effect ...
Songyi Yoo +2 more
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1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design [PDF]
IEEE Journal of the Electron Devices Society, 2015 In this work we propose and demonstrate the use of a Tunnel FET (TFET) as capacitorless DRAM cell based on TCAD simulations and experiments. We report more experimental results on Tunnel FETs implemented as a double-gate (DG) fully-depleted Silicon-On ...
Arnab Biswas, Adrian M. Ionescu
doaj +2 more sources
Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory [PDF]
Nanoscale Research Letters, 2022 Three-terminal (3-T) thyristor random-access memory is explored for a next-generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate–cathode voltage (V GC,ST ...
Hyangwoo Kim +6 more
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Capacitorless One-Transistor Dynamic Random-Access Memory with Novel Mechanism: Self-Refreshing [PDF]
NanomaterialsIn this paper, we propose for the first time a self-refreshing mechanism in a junctionless field-effect transistor (JLFET) based on one-transistor dynamic random-access memory (1T-DRAM) with a silicon-on-insulator (SOI) structure.
Sang Ho Lee +3 more
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1 Transistor‐Dynamic Random Access Memory as Synaptic Element for Online Learning
Advanced Intelligent SystemsThe rapid advancements in the field of autonomous systems have led to a significant demand for artificial‐intelligence‐of‐things (AIoT) edge‐compatible neuromorphic training accelerators with continual/online learning capability.
MD Yasir Bashir +2 more
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Memory Characteristics of 1T-DRAM Cell by Channel Structure [PDF]
Journal of the Korean Institute of Electrical and Electronic Material Engineers, 2012 We fabricated fully depleted (FD) SOI-based 1T-DRAM cells with planar channel or recessed channel and the electrical characteristics were investigated. In particular, the dependence of memory operating mode on the channel structure of 1T-DRAM cells was evaluated.
Ki-Hyun Jang +3 more
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Comparative Study of Steep Switching Devices for 1T Dynamic Memory [PDF]
Tecnología en MarchaThis work focuses on understanding the operation and performance of various steep switching devices (subthreshold slope sub 60 mV/decade), namely Thin-Capacitively Coupled Thyristor (TCCT), Field Effect Diode (FED), Zero sub-threshold swing and Zero ...
Nupur Navlakha +3 more
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Non-destructive read 1T-DRAM with p–n junction gate for overcoming scaling limitations [PDF]
AIP AdvancesThis paper presents a p–n junction gate dynamic random-access memory (DRAM) architecture that addresses the scaling limitations of conventional 1T1C DRAM and the structural challenges of capacitor-less 1T0C and 2T0C designs. The proposed device employs a
Eungi Hwang +5 more
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Capacitorless 1T DRAM Sensing Scheme With Automatic Reference Generation
IEEE Journal of Solid-State Circuits, 2006 To perform a current sensing in capacitorless 1-transistor (1T) DRAMs on SOI, we have developed a sensing scheme with automatic reference generation. The reference current is generated by an adjustable current source. The electrical calibration of the reference current source is performed using a digital-to-analog converter and a successive ...
M. Blagojevic +6 more
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