Results 41 to 50 of about 930 (217)

Advances in Solid State Circuit Technologies [PDF]

, 2021
This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies.

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2D-TCAD Simulation on Retention Time of Z2FET for DRAM Application [PDF]

, 2017
Traditional memory devices are facing more challenges due to continuous down-scaling. 6T-SRAM suffers from variability [1-2] and reliability [3-4] issues, which introduce cell stability problems.
Adamu-Lema, F., Asenov, A., Cheng, B., Duan, M., Gamiz, F., Georgiev, V.P., Millar, C., Navarro, C., Wang, X.   +8 more
core   +1 more source

Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

Memories - Materials, Devices, Circuits and Systems, 2023
TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust ...
Koji Sakui, Yisuo Li, Masakazu Kakumu, Kenichi Kanazawa, Iwao Kunishima, Yoshihisa Iwata, Nozomu Harada   +6 more
doaj   +1 more source

Modelling and simulation of advanced semiconductor devices [PDF]

, 2017
This paper presents a modelling and simulation study of advanced semiconductor devices. Different Technology Computer Aided Design approaches and models, used in nowadays research are described here.
Adamu-Lema, Fikru, Al-Ameri, T., Asenov, Asen, Berrada, Salim, Duan, Meng, Georgiev, Vihar, Lee, Jaehyun   +6 more
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Optoelectronic Devices for In-Sensor Computing. [PDF]

Adv Mater
The raw data obtained directly from sensors in the noisy analogue domain is often unstructured, which lacks a predefined format or organization and does not conform to a specific data model. Optoelectronic devices for in‐sensor visual processing can integrate perception, memory, and processing functions in the same physical units, which can compress ...
Ren Q, Zhu C, Ma S, Wang Z, Yan J, Wan T, Yan W, Chai Y.   +7 more
europepmc   +2 more sources

A Study on Semiconductor Memory Cells Using CMOS- Technologies in Digital Electronics [PDF]

, 2023
The CMOS technology is known for low threshold voltage high density and high performance. The electronic circuit or components density has increased daily in a single chip by employing VLSI design.
Rohit Kumar
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Investigation of thin gate-stack Z2-FET devices as capacitor-less memory cells [PDF]

, 2019
Thin-oxide Z2-FET cells operating as capacitor-less DRAM devices are experimentally demonstrated. Both the retention time and memory window demonstrate the feasibility of implementing this cell in advanced 28 nm node FD SOI technology.
Bawedin, Maryline, Cristoloveanu, Sorin, Galy, Philippe, Gámiz Pérez, Francisco Jesús, Kim, Kim, Yong Tae, Lee, Kyunghwa, Márquez González, Carlos, Navarro Moral, Carlos, Navarro Moral, Santiago, Parihar, Mukta Singh, Park, Hyungjin   +11 more
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Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact [PDF]

, 2022
This work was supported by the Spanish under Grant MCIN/AEI/10.13039/501100011033 and Project PID2019-103869RB-C33.This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge ...
Calomarde, Antonio, Gámiz Pérez, Francisco Jesús   +1 more
core   +4 more sources

Extended analysis of the Z2-FET: Operation as capacitor-less eDRAM [PDF]

, 2017
This article has been accepted for publication by IEEE "Navarro Moral, C.; et al. Extended analysis of the Z2-FET: Operation as capacitor-less eDRAM. IEEE Transactions on Electron Devices, 64(11): 4486-4491 (2017).
Adamu-Lema, Fikru, Asenov, Asen, Barbe, Jean-Charles, Bawedin, Maryline, Cheng, Binjie, Cristoloveanu, Sorin, Duan, Meng, El Dirani, Hassam, Fonteneau, Pascal, Galy, Philippe, Gámiz Pérez, Francisco Jesús, Karg, Sigfried, Kim, Yong Tae, Lacord, Joris, Le Royer, Cyrille, Millar, Campbell, Navarro Moral, Carlos, Parihar, Mukta Singh, Rodríguez Santiago, Noel, Wells, Paul   +19 more
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3D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs [PDF]

, 2019
3-D numerical technology computer-aided design simulations, based on experimental results, are performed to study the origin of the large Z 2 -FET dynamic random access memory (DRAM) memory cell-to-cell variability on fully depleted silicon-on-insulator (
Galy, Philippe, Gámiz Pérez, Francisco Jesús, Márquez González, Carlos, Navarro Moral, Carlos, Navarro Moral, Santiago, Padilla De la Torre, José Luis   +5 more
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