Results 171 to 180 of about 1,500,059 (236)

CDSAXS study of 3D NAND channel hole etch pattern edge effects and etched hole pattern variance

Advanced Lithography
Critical dimension small angle X-ray scattering (CDSAXS) has been shown capable of measuring 3D NAND deep-etch structures, like channel holes and wordline cut for CD, CD profile, and center-line-shift (or tilt) non-destructively. New 3D NAND flash design
Jin Zhang, Tian Lan, Ying Gao, Osman Sorkhabi, Yung-Yi Lin, Maggie Li, Dave Oak, Zhengquan Tan   +7 more
semanticscholar   +1 more source

3D VG-Type NAND Flash Memories

2016
The common feature among the different 3D NAND solutions is constituted by very deep vertical (z direction) etching steps that define the Flash cells geometries simultaneously. Transistor geometries are formed by the deep trench through a multiple polysilicon/oxide stack.
openaire   +1 more source

SiGe/Si Heterojunction Drain Transistor for Faster 3D NAND Flash Memory Erase

International Memory Workshop
Some 3D NAND flash memory technologies utilize the phenomenon of Gate Induced Drain Leakage (GIDL) for erase operation. As the number of memory cells stacked in a 3D NAND string increases, larger GIDL current is needed to maintain the same erase speed ...
Dasom Lee, Tsu-Jae King Liu
semanticscholar   +1 more source

Etch Challenges for 3D NAND Flash Technology

ECS Meeting Abstracts, 2014
Current 2D NAND scaling is approaching technology limitation in both lithography and device performance arena. To address the lithography challenges at the 1x nodes and the well-known scaling issues associated with planar NAND, 3D flash technology is being developed and is expected to greatly reduce the lithography burden albeit shifting it to ...
Anisul Haque Khan, Sunil Srinivasan, Jinhan Choi, Amulya Athayde, Raman Achutharaman   +4 more
openaire   +1 more source

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array

IEICE Transactions on Electronics, 2009
We propose a 3-dimensional terraced NAND flash memory. It has a vertical channel so it is possible to make a long enough channel in 1F 2 size. And it has 3-dimensional structure whose channel is connected vertically along with two stairs. So we can obtain high density as in the stacked array structure, without silicon stacking process.
Yoon KIM, Seongjae CHO, Gil Sung LEE, Il Han PARK, Jong Duk LEE, Hyungcheol SHIN, Byung-Gook PARK   +6 more
openaire   +1 more source

Improving Block Management in 3D NAND Flash SSDs with Sub-Block First Write Sequencing

ACM Great Lakes Symposium on VLSI
Continual vertical scaling in 3D NAND flash solid-state drives (SSDs) results in larger memory blocks, causing performance degradation due to big-block management issues.
Matchima Buddhanoy, Kamil Khan, Aleksandar Milenkovic, S. Pasricha, B. Ray   +4 more
semanticscholar   +1 more source

Etching of Silicon Nitride in 3D NAND Structures

ECS Meeting Abstracts, 2015
3D NAND structures present a unique difficulty in semiconductor device manufacturing.  One method of production consists of cylindrical structures made of alternating layers of silicon dioxide (SiO2) and silicon nitride (SiN) with a core of SiO2.  As part of the device manufacturing process the SiN is etched away, leaving the SiO2 core with disc-shaped
Derek Bassett, Wallace Printz, Takahiro Furukawa   +2 more
openaire   +1 more source

Exploring the Reliability Limits for the Z-Pitch Scaling of Molybdenum Inter-Word Line Oxides in 3D NAND

IEEE International Reliability Physics Symposium
In this work, we evaluate the scaling limits of inter-word line oxides for 3D NAND Flash devices. We test different oxide stacks by mimicking the stacked architecture using planar capacitors, in combination with Mo electrodes.
D. Tiernc, A. Arreghini, Alicja Lesniewska, Y. Jeong, M. H. V. D. Veen, J. Stiers, N. Bazzazian, I. Ciofi, G. V. D. Bosch, M. Rosmeulen   +9 more
semanticscholar   +1 more source

Modeling and Optimization of Advanced 3D NAND Memory

2020 Device Research Conference (DRC), 2020
Development of a new complex technology such as 3D NAND requires significant efforts in terms of materials screening, process tuning, and device design leading to fabrication and characterization of many test wafers with significant time-to-market cost. In this context, modeling can help accelerate 3D NAND technology development.
Mehdi Saremi, Ashish Pal, Liu Jiang, El Mehdi Bazizi, Helen Lee, Xi-Wei Lin, Blessy Alexander, Buvna Ayyagari-Sangamalli   +7 more
openaire   +1 more source

Life-after-Death: Exploring Thermal Annealing Conditions to Enhance 3D NAND SSD Endurance

USENIX Workshop on Hot Topics in Storage and File Systems
In this paper, we evaluate thermal annealing effects on the endurance of commercial off-the-shelf (COTS) 3D NAND flash memory beyond its end-of-life. We systematically evaluate the effects of anneal duration, anneal temperature, and state of the memory ...
Matchima Buddhanoy, S. Pasricha, Biswajit Ray   +2 more
semanticscholar   +1 more source