Results 181 to 190 of about 1,500,059 (236)
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Experimental Segmentation of Vertical Charge Loss Mechanisms in Charge Trap-Based 3D NAND Arrays
IEEE International Reliability Physics SymposiumIn this work, we provide a detailed characterization and modeling of the physical mechanisms responsible for the vertical loss (VL) of charge in charge trap (CT) 3D NAND flash arrays.
L. Chiavarone +3 more
semanticscholar +1 more source
International Memory Workshop
A novel 3D filtering cube is proposed in 3D-NAND flash for computational SSD to execute 3D in-memory-search (3D IMS) function at ultra-high search bandwidth.
P. Tseng +9 more
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A novel 3D filtering cube is proposed in 3D-NAND flash for computational SSD to execute 3D in-memory-search (3D IMS) function at ultra-high search bandwidth.
P. Tseng +9 more
semanticscholar +1 more source
3D NAND Flash Status and Trends
2022 IEEE International Memory Workshop (IMW), 2022Lars Heineck, Jin Liu
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Optimal etch recipe prediction for 3D NAND structures
Advanced Etch Technology for Nanopatterning IX, 2020We present a model-based experimental design methodology for accelerating 3D etch optimization with demonstration on 3D NAND structures. The design and optimization of etch recipes for such 3D structures face significant challenges requiring costly and time-consuming experiments in order to achieve the required tolerances.
Leandro Medina +3 more
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2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
In this work, we systematically studied the effective resistivity of word lines (WLs) of 3D NAND memory. We fabricated narrow and high-aspect-ratio wires in the similar way to the WL forming process of replacement-gate NAND and measured the resistivity ...
H. Terada +6 more
semanticscholar +1 more source
In this work, we systematically studied the effective resistivity of word lines (WLs) of 3D NAND memory. We fabricated narrow and high-aspect-ratio wires in the similar way to the WL forming process of replacement-gate NAND and measured the resistivity ...
H. Terada +6 more
semanticscholar +1 more source
A DTCO Framework for 3D NAND Flash Readout
2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)To continue increasing the storage density of 3D NAND flash memories, new technology options need to be evaluated early on. This work presents a unique predictive parametric framework for Multi-Level Cell 3D NAND Flash read operation at the array level ...
Mattia Gerardi +6 more
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Scaling directions for 2D and 3D NAND cells
2012 International Electron Devices Meeting, 2012This paper describes NAND cell scaling directions for 20nm and beyond. Many of the 2D NAND cell scaling challenges can be resolved by a planar floating gate (FG) cell. Scaling directions and key technology requirements for 3D NAND are also discussed.
Akira Goda, Krishna Parat
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Reinforcement Learning-Based Read Performance Throttling to Enhance Lifetime of 3D NAND SSD
IEEE Non-Volatile Memory System and Applications SymposiumWith high storage density and low cost per bit, 3D NAND flash has dominated the market of modern solid-state drives (SSDs). Nevertheless, the growing number of stacked layers and the evolving multi-bits-per-cell technology of 3D NAND flash have led to ...
Yong-Cheng Liaw +2 more
semanticscholar +1 more source
Pure-Metal Replacement Gate for Reliable 30 nm Pitch Scaled 3D NAND Flash
International Memory WorkshopWe demonstrate the integration of Molybdenum as "a pure metal gate" in a record 30 nm z-pitch 3D NAND device by adopting a barrierless replacement metal gate (RMG) process. We also propose and demonstrate an in-memory-hole high-k (HK) liner to extend the
S. Rachidi +9 more
semanticscholar +1 more source
Copper interconnect topography simulation in 3D NAND designs
Design-Process-Technology Co-optimization for Manufacturability XIII, 2019Vertical NAND (3D NAND) designs provide unprecedented improvements in input/output (I/O) performance and storage density, but require additional analysis to ensure manufacturing and market success. While 3D stacked architectures greatly reduce chip area at advanced technology nodes, greater topology uniformity is essential, not only for inter-layers ...
Yang Li +11 more
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