Results 31 to 40 of about 529 (162)
IEEE Journal of the Electron Devices Society, 2021 Reading data at a temperature which different from writing can cause a large number of failed bits in 3D NAND Flash memory. In this work, the threshold voltage (Vth) temperature effect of 3D NAND flash memory cell was investigated and a method was ...
Dan Wu +4 more
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Memories - Materials, Devices, Circuits and Systems, 2023 In this paper, we propose a gate-all-around with back-gate (GAAB) 3D NAND flash memory structure for high performance and reliability. First, in the selected string, we confirmed that the proposed structure can improve program performance using negative ...
Jae-Min Sim +6 more
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IEEE Journal of the Electron Devices Society, 2021 For triple-level or quad-level 3D NAND flash memory, narrowing the Vth distribution of each state without influencing page program performance is one of the challenges.
Zhichao Du +6 more
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Electronics Letters, 2022 This letter presents an efficient built‐in error detection methodology for 3D NAND flash memories, in which fast page‐oriented data comparison and column parallel error detection are firstly proposed.
HM. Cao +5 more
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Investigation of Re-Program Scheme in Charge Trap-Based 3D NAND Flash Memory
IEEE Journal of the Electron Devices Society, 2021 Early retention or initial threshold voltage shift (IVS) is one of the key reliability challenges in charge trapping memory (CTM) based 3D NAND flash. Re-program scheme was introduced in quad-level-cell (QLC) NAND (Shibata et al., 2007, Lee et al., 2018,
Ting Cheng +13 more
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Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory
IEEE Access, 2021 In charge-trap (CT) three-dimensional (3D) NAND flash memory, the transition layer between Si3N4 CT layer and SiO2 tunneling layer is inevitable, and the defects in the transition layer are expected to cause both lateral and vertical charge loss.
Fei Wang +3 more
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A Behavioral Compact Model of 3D NAND Flash Memory
CoRR, 2018 We present a behavioral compact model of 3D NAND flash memory for integrated circuits and system-level applications. This model is easy to implement, computationally efficient, fast, accurate and effectively accounts for the different parasitic capacitance coupling effects applicable to the 3D geometry of the vertical channel Macaroni body charge-trap ...
Shubham Sahay, Dmitri B. Strukov
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IEEE Access, 2023 To achieve high density, the spacer length of three dimensional (3D) NAND device has been scaled down. When the program/erase cycle repeats, problems such as electrons accumulation in the inter-cell region are occurred. To solve this problem, a method of
Yun-Jae Oh +4 more
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Analysis of High-Temperature Data Retention in 3D Floating-Gate nand Flash Memory Arrays
IEEE Journal of the Electron Devices Society, 2023 In this paper, we present a detailed experimental investigation of high-temperature data retention in 3D floating-gate NAND Flash memory arrays. Data reveal that charge detrapping from the cell tunnel oxide and depassivation of traps in the string ...
Gerardo Malavena +4 more
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A Unified Flash Memory Platform for Mode‐Adaptive and Robust AI Computation
Advanced Science, EarlyView.A unified AND‐type flash memory platform enables both transistor‐mode and capacitor‐mode computing‐in‐memory operations within the same device structure. By selectively switching the sensing mode through peripheral reconfiguration, the platform provides adaptable trade‐offs between computational accuracy, robustness, and energy efficiency for AI ...
Dayeon Yu +6 more
wiley +1 more source