Results 41 to 50 of about 5,453 (181)
Investigation of Re-Program Scheme in Charge Trap-Based 3D NAND Flash Memory
IEEE Journal of the Electron Devices Society, 2021 Early retention or initial threshold voltage shift (IVS) is one of the key reliability challenges in charge trapping memory (CTM) based 3D NAND flash. Re-program scheme was introduced in quad-level-cell (QLC) NAND (Shibata et al., 2007, Lee et al., 2018,
Ting Cheng +13 more
doaj +1 more source
Survey of storage systems for high-performance computing [PDF]
, 2018 In current supercomputers, storage is typically provided by parallel distributed file systems for hot data and tape archives for cold data. These file systems are often compatible with local file systems due to their use of the POSIX interface and ...
Alforov, Yevhen +6 more
core +1 more source
Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory
IEEE Access, 2021 In charge-trap (CT) three-dimensional (3D) NAND flash memory, the transition layer between Si3N4 CT layer and SiO2 tunneling layer is inevitable, and the defects in the transition layer are expected to cause both lateral and vertical charge loss.
Fei Wang +3 more
doaj +1 more source
Optimization and evaluation of variability in the programming window of a flash cell with molecular metal-oxide storage [PDF]
, 2014 We report a modeling study of a conceptual nonvolatile memory cell based on inorganic molecular metal-oxide clusters as a storage media embedded in the gate dielectric of a MOSFET.
Asenov, Asen +5 more
core +3 more sources
A Behavioral Compact Model of 3D NAND Flash Memory
CoRR, 2018 We present a behavioral compact model of 3D NAND flash memory for integrated circuits and system-level applications. This model is easy to implement, computationally efficient, fast, accurate and effectively accounts for the different parasitic capacitance coupling effects applicable to the 3D geometry of the vertical channel Macaroni body charge-trap ...
Shubham Sahay, Dmitri B. Strukov
openaire +2 more sources
IEEE Access, 2023 To achieve high density, the spacer length of three dimensional (3D) NAND device has been scaled down. When the program/erase cycle repeats, problems such as electrons accumulation in the inter-cell region are occurred. To solve this problem, a method of
Yun-Jae Oh +4 more
doaj +1 more source
Analysis of High-Temperature Data Retention in 3D Floating-Gate nand Flash Memory Arrays
IEEE Journal of the Electron Devices Society, 2023 In this paper, we present a detailed experimental investigation of high-temperature data retention in 3D floating-gate NAND Flash memory arrays. Data reveal that charge detrapping from the cell tunnel oxide and depassivation of traps in the string ...
Gerardo Malavena +4 more
doaj +1 more source
Nonvolatile memory with molecule-engineered tunneling barriers
, 2008 We report a novel field-sensitive tunneling barrier by embedding C60 in SiO2 for nonvolatile memory applications. C60 is a better choice than ultra-small nanocrystals due to its monodispersion.
Baik S. J. +10 more
core +1 more source
Coding scheme for 3D vertical flash memory
, 2015 Recently introduced 3D vertical flash memory is expected to be a disruptive technology since it overcomes scaling challenges of conventional 2D planar flash memory by stacking up cells in the vertical direction.
Bandic, Zvonimir +4 more
core +1 more source
Evolution of Materials and Device Stacks for HfO2‐Based Ferroelectric Memories
Advanced Materials Interfaces, EarlyView.This review summarizes engineering strategies for HfO2 based ferroelectric memories with focus on FeCAP and FeFET structures. It describes how dopant design, stress effects, and interface engineering improve the bulk ferroelectric response. It further discusses how channel engineering supports reliable memory characteristics and scalable integration ...
Eunjin Kim, Jiyong Woo
wiley +1 more source