Investigation of the Connection Schemes between Decks in 3D NAND Flash. [PDF]
Dual-deck stacking technology is an effective solution for solving the contradiction between the demand for increasing storage layers and the challenge of the deep hole etching process in 3D NAND flash. The connection scheme between decks is a key technology for the dual-deck structure.
Jia J, Jin L, You K, Zhu A.
europepmc +4 more sources
Adaptive Bitline Voltage Countermeasure for Neighbor Wordline Interference in 3D NAND Flash Memory-Based Sensors [PDF]
Three-dimensional NAND flash memory is widely used in sensor systems as an advanced storage medium that ensures system stability through fast data access. However, in flash memory, as the number of cell bits increases and the process pitch keeps scaling,
Hanshui Fan +6 more
doaj +2 more sources
Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash [PDF]
The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes.
Tao Yang +8 more
doaj +2 more sources
Effect of Noncircular Channel on Distribution of Threshold Voltage in 3D NAND Flash Memory [PDF]
The instability in threshold voltage (VTH) and charge distributions in noncircular cells of three-dimensional (3D) NAND flash memory are investigated.
Donghyun Go +6 more
doaj +2 more sources
Optimal Energetic-Trap Distribution of Nano-Scaled Charge Trap Nitride for Wider Vth Window in 3D NAND Flash Using a Machine-Learning Method [PDF]
A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (Vth) window, which is crucial for NAND operation.
Kihoon Nam +10 more
doaj +2 more sources
Wordline Input Bias Scheme for Neural Network Implementation in 3D-NAND Flash [PDF]
In this study, we propose a neuromorphic computing system based on a 3D-NAND flash architecture that utilizes analog input voltages applied through wordlines (WLs).
Hwiho Hwang +3 more
doaj +2 more sources
Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices
We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field.
Alessandro Sottocornola Spinelli +2 more
exaly +3 more sources
Modeling methodology for thermo-structural analysis of V-NAND flash memory structure [PDF]
This study proposes modeling methodology based on a continuous model for conducting thermo-electric-structural analyses of V-NAND flash memory structure under the Joule heating effect.
Yongha Kim, Seungjun Ryu, Sungryung Lee
doaj +2 more sources
Controlling the Carrier Injection Efficiency in 3D Nanocrystalline Silicon Floating Gate Memory by Novel Design of Control Layer [PDF]
Three-dimensional NAND flash memory with high carrier injection efficiency has been of great interest to computing in memory for its stronger capability to deal with big data than that of conventional von Neumann architecture.
Hongsheng Hu +8 more
doaj +2 more sources
Impact of Program–Erase Operation Intervals at Different Temperatures on 3D Charge-Trapping Triple-Level-Cell NAND Flash Memory Reliability [PDF]
Three-dimensional charge-trapping (CT) NAND flash memory has attracted extensive attention owing to its unique merits, including huge storage capacities, large memory densities, and low bit cost.
Xuesong Zheng +6 more
doaj +2 more sources

