Results 71 to 80 of about 529 (162)

Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories

open access: yesACM Transactions on Architecture and Code Optimization
With the development of NAND flash memories’ bit density and stacking technologies, while storage capacity keeps increasing, the issue of reliability becomes increasingly prominent. Low-density parity check (LDPC) code, as a robust error-correcting code, is extensively employed in flash memory.
Qiao Li 0001   +9 more
openaire   +1 more source

Trade-off of Program Speed and Z-Interference According to Trap Position in 3-D NAND Flash Memory

open access: yesIEEE Journal of the Electron Devices Society
This work proposes a distance-dependent trap model to overcome the limitations of conventional Technology Computer-Aided Design (TCAD) models, which fail to accurately represent the non-uniform charge distribution resulting from electron energy ...
Gyuhyeon Lee   +4 more
doaj   +1 more source

Optimal Energetic-Trap Distribution of Nano-Scaled Charge Trap Nitride for Wider Vth Window in 3D NAND Flash Using a Machine-Learning Method. [PDF]

open access: yesNanomaterials (Basel), 2022
Nam K   +10 more
europepmc   +1 more source

Understanding the Origin of Metal Gate Work Function Shift and Its Impact on Erase Performance in 3D NAND Flash Memories. [PDF]

open access: yesMicromachines (Basel), 2021
Ramesh S   +10 more
europepmc   +1 more source

A physics-guided surrogate modeling framework for RDF-dominated variability and bit-error rate analysis of 3D NAND flash memory

open access: yesDiscover Applied Sciences
Three-dimensional (3D) NAND flash memory has become the dominant non-volatile storage technology due to its high density and scalability. However, aggressive vertical stacking introduces significant threshold-voltage (VT) variability that affects device ...
Dikendra Kumar Verma   +2 more
doaj   +1 more source

A String-Select-Line Separation Patterning Scheme for Low Voltage and High-Speed Program Operation in 3D NAND Flash Memory With Separated Source-Line

open access: yesIEEE Access
In this paper, we propose a novel String-Select-Line Separation Patterning (SSP) scheme designed for low voltage and high-speed program operation in 3D NAND flash memory structures with a separated Source-Line (SL).
Jae-Min Sim, Hakyeong Kim, Yun-Heub Song
doaj   +1 more source

Unveiling the Hybrid‐Channel (poly‐Si/IGO) Structure for 3D NAND Flash Memory for Improving the Cell Current and GIDL‐Assisted Erase Operation

open access: yesSmall Structures
Oxide semiconductors (OSs) are promising materials for NAND flash memory, offering the advantages of high field‐effect mobility and superior large‐area uniformity but suffering from low thermal stability, trade‐off between mobility and stability, and the
Su‐Hwan Choi   +15 more
doaj   +1 more source

Ultra-high bit density liquid-state colloidal memory

open access: yesMemories - Materials, Devices, Circuits and Systems
Despite the historical growth of storage technologies, such as 3D NAND flash, hard disk drives, and tape storage, each of them is facing inherent scaling limitations. 3D NAND flash suffers from rising costs due to the complex 3D fabrication process.
Bing-Yang Shih   +12 more
doaj   +1 more source

A Study of Invalid Programming in 3D QLC NAND Flash Memories

open access: yesProceedings of the 15th ACM Workshop on Hot Topics in Storage and File Systems, 2023
Hongyang Dang   +3 more
openaire   +1 more source

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