Results 91 to 100 of about 5,453 (181)

Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories

ACM Transactions on Architecture and Code Optimization
With the development of NAND flash memories’ bit density and stacking technologies, while storage capacity keeps increasing, the issue of reliability becomes increasingly prominent. Low-density parity check (LDPC) code, as a robust error-correcting code, is extensively employed in flash memory.
Qiao Li 0001, Yu Chen, Guanyu Wu, Yajuan Du, Min Ye, Xinbiao Gan, Jie Zhang 0048, Zhirong Shen, Jiwu Shu, Chun Xue 0001   +9 more
openaire   +1 more source

NASA Electronic Parts and Packaging (NEPP) Program Plans [PDF]

This presentation provides an overview of the NEPP ...
Label, Kenneth A., Sampson, Michael J.
core   +1 more source

Understanding the Origin of Metal Gate Work Function Shift and Its Impact on Erase Performance in 3D NAND Flash Memories. [PDF]

Micromachines (Basel), 2021
Ramesh S, Ajaykumar A, Ragnarsson LÅ, Breuil L, El Hajjam GK, Kaczer B, Belmonte A, Nyns L, Soulié JP, Van den Bosch G, Rosmeulen M.   +10 more
europepmc   +1 more source

Incremental Pulse-Width Erase (IPWE) Scheme for Fast and Variation-Tolerant GIDL Erase of 3D NAND Flash

Micromachines
In this work, we propose an incremental pulse-width erase (IPWE) scheme for fast and variation-tolerant gate-induced drain leakage (GIDL) erase of 3D NAND flash.
Youngjun Park, Wonbo Shim
doaj   +1 more source

A String-Select-Line Separation Patterning Scheme for Low Voltage and High-Speed Program Operation in 3D NAND Flash Memory With Separated Source-Line

IEEE Access
In this paper, we propose a novel String-Select-Line Separation Patterning (SSP) scheme designed for low voltage and high-speed program operation in 3D NAND flash memory structures with a separated Source-Line (SL).
Jae-Min Sim, Hakyeong Kim, Yun-Heub Song
doaj   +1 more source

Unveiling the Hybrid‐Channel (poly‐Si/IGO) Structure for 3D NAND Flash Memory for Improving the Cell Current and GIDL‐Assisted Erase Operation

Small Structures
Oxide semiconductors (OSs) are promising materials for NAND flash memory, offering the advantages of high field‐effect mobility and superior large‐area uniformity but suffering from low thermal stability, trade‐off between mobility and stability, and the
Su‐Hwan Choi, Jae‐Min Sim, Jeongmin Shin, Seong‐Hwan Ryu, Taewon Hwang, So Young Lim, Hye‐Jin Oh, Jae‐Hyeok Kwag, Jun‐Yeoub Lee, Ki‐Cheol Song, Yeonhee Lee, Minju Song, Junghwan Kim, Chang‐Kyun Park, Yun‐Heub Song, Jin‐Seong Park   +15 more
doaj   +1 more source

Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory

IEEE Journal of the Electron Devices Society
In this paper, we propose a low-power stack-level programming scheme for ultrahigh stack 3D NAND flash memory. As the number of word lines (WLs) increases beyond 300 layers, the increased pass voltage leads to excessive power consumption and reliability ...
Kyungmin Lee, Gunwook Yoon, Seung Jae Baik, Myounggon Kang   +3 more
doaj   +1 more source

Overview of emerging nonvolatile memory technologies [PDF]

, 2014

core   +1 more source

A Study of Invalid Programming in 3D QLC NAND Flash Memories

Proceedings of the 15th ACM Workshop on Hot Topics in Storage and File Systems, 2023
Hongyang Dang, Xiangyu Yao, Zheng Wan, Qiao Li 0001   +3 more
openaire   +1 more source

Balancing Page Endurance Variation Between Layers to Extend 3D NAND Flash Memory Lifetime. [PDF]

Micromachines (Basel)
Wang J, Fan Y, Du Y, Huang S, Wan Y.
europepmc   +1 more source