Results 91 to 100 of about 1,894,725 (194)

Bit error rate estimation of modern 3D-NAND flash partitions in space mass memories

A system level bit error rate estimation of a 3D-NAND Flash Partition for different radiation environments and operating modes (SLC/TLC) is performed.
Grürmann, Kai, Rust, Jochen, Wyrwoll, Vanessa, Dirkes, Timo, Poppe, Björn, Spindeldreier, Christian   +5 more
core   +1 more source

layer granularity refresh for improving performance and lifetime of 3D NAND flash memory

, 2023
학위논문(석사) - 한국과학기술원 : 전산학부, 2023.2,[iv, 33 p. :]NAND flash refresh schemes have been proposed to mitigate retention errors by remapping pages before excessive errors occur in them.
Kim, Hyungsoon
core  

Using 3D NAND Flash Memory in SSDs to Improve Storage and Performance [PDF]

, 2020
[excerpt] In the rapid development process of data storage, 3D NAND is the next generation of this technology in which the semiconductor flash cells of the solid-state drive (SSD) are stacked vertically to increase storage density and read / write ...
Welch, Daniel
core  

A Novel Program Scheme for Z-Interference Improvement in 3D NAND Flash Memory. [PDF]

Micromachines (Basel), 2023
Jia J, Jin L, Jia X, You K.
europepmc   +1 more source

Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND Flash

, 2019
3D charge trap (CT) triple-level cell (TLC) NAND flash gradually becomes a mainstream storage component due to high storage capacity and performance, but introducing a concern about reliability.
Fei Wu, Meng Zhang, Wu, Fei,, Xiangfeng Lu, Changsheng Xie, Zhang, Meng,, Lu, Xiangfeng,, Liu, Weihua,, Xie, Changsheng,, Yifei Wang, Weihua Liu, Zhonghai Lu, Lu, Zhonghai,, Wang, Yifei,   +13 more
core   +1 more source

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory. [PDF]

Micromachines (Basel), 2023
You K, Jin L, Jia J, Huo Z.
europepmc   +1 more source

Optimizing Cell Structure to Improve Cell Characteristics in IGZO Channel-Based 3D NAND Flash With p-Type Gate

IEEE Access
For the first time, a novel IGZO channel-based 3D NAND Flash structure with an embedded p-type poly-Si injection layer is proposed, using integrated structural, material, and operational modifications to address the limitations of the conventional IGZO ...
Sungho Park, Youngho Jung, Daewoong Kang
doaj   +1 more source

Characterization of TLC 3D-NAND Flash Endurance through Machine Learning for LDPC Code Rate Optimization

, 2017
The advent of the 3D-NAND Flash memories introduced significant issues in terms of characterization and system-level optimization that can be performed to increase the memory reliability over its lifetime.
Cristian Zambelli, Evelina Lamma, Alessia Marelli, Giuseppe Cancelliere, Cancelliere, Giuseppe, LAMMA, Evelina, Marelli, Alessia, RIGUZZI, Fabrizio, Micheloni, Rino, Rino Micheloni, ZAMBELLI, Cristian, OLIVO, Piero, Fabrizio Riguzzi, Piero Olivo   +13 more
core   +1 more source

Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories

ACM Transactions on Architecture and Code Optimization
With the development of NAND flash memories’ bit density and stacking technologies, while storage capacity keeps increasing, the issue of reliability becomes increasingly prominent. Low-density parity check (LDPC) code, as a robust error-correcting code, is extensively employed in flash memory.
Qiao Li 0001, Yu Chen, Guanyu Wu, Yajuan Du, Min Ye, Xinbiao Gan, Jie Zhang 0048, Zhirong Shen, Jiwu Shu, Chun Xue 0001   +9 more
openaire   +2 more sources

Reliability of NAND Flash Memories

, 2010
The continuous demand for NAND flash memories with higher performance and storage capabilities pushes the manufactures towards the limits of present technologies and to explore new solutions, both from the physical and the architectural point of view ...
ZAMBELLI, Cristian, OLIVO, Piero, CHIMENTON, Andrea   +2 more
core