Results 101 to 110 of about 1,894,725 (194)
Novel cell-level erase for 3D NAND Flash memory
With advances in AI and the widespread adoption of NAND Flash technology imposing increasingly stringent performance requirements, conventional erase was unable to provide precise erasing in NAND Flash storage systems.
Guokun Ma +7 more
core +1 more source
International audienceBulk bitwise operations, i.e., bitwise operations on large bit vectors, are prevalent in a wide range of important application domains, including databases, graph processing, genome analysis, cryptography, and hyper-dimensional ...
Park, Jisung +8 more
core
수직 3D NAND Flash 메모리 신뢰성에 관한 전산모사 및 특성분석
DoctorTo overcome the limitations of scaling down in the 2D planar NAND flash memory, 3D vertical NAND flash memory attracted attention, and many researches and mass production were carried out.
오현관
core
Optimal Energetic-Trap Distribution of Nano-Scaled Charge Trap Nitride for Wider Vth Window in 3D NAND Flash Using a Machine-Learning Method. [PDF]
Nam K +10 more
europepmc +1 more source
Understanding the Origin of Metal Gate Work Function Shift and Its Impact on Erase Performance in 3D NAND Flash Memories. [PDF]
Ramesh S +10 more
europepmc +1 more source
In this paper, we propose a novel String-Select-Line Separation Patterning (SSP) scheme designed for low voltage and high-speed program operation in 3D NAND flash memory structures with a separated Source-Line (SL).
Jae-Min Sim, Hakyeong Kim, Yun-Heub Song
doaj +1 more source
Three-dimensional (3D) NAND flash memory has become the dominant non-volatile storage technology due to its high density and scalability. However, aggressive vertical stacking introduces significant threshold-voltage (VT) variability that affects device ...
Dikendra Kumar Verma +2 more
doaj +1 more source
Trade-off of Program Speed and Z-Interference According to Trap Position in 3-D NAND Flash Memory
This work proposes a distance-dependent trap model to overcome the limitations of conventional Technology Computer-Aided Design (TCAD) models, which fail to accurately represent the non-uniform charge distribution resulting from electron energy ...
Gyuhyeon Lee +4 more
doaj +1 more source
In this paper, we propose a low-power stack-level programming scheme for ultrahigh stack 3D NAND flash memory. As the number of word lines (WLs) increases beyond 300 layers, the increased pass voltage leads to excessive power consumption and reliability ...
Kyungmin Lee +3 more
doaj +1 more source
Cryogenic Investigation of Vertical Charge Loss in 3D NAND Flash Memories
We present a detailed investigation of vertical charge loss in 3D NAND Flash memories down to the deep cryogenic regime. The extremely wide temperature range explored allows to derive clear experimental evidence for some important aspects of the vertical
D. G. Refaldi +5 more
core +1 more source

