Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic [PDF]
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Chen, Shuo Han
core
NASA Electronic Parts and Packaging (NEPP) Program Plans [PDF]
This presentation provides an overview of the NEPP ...
Label, Kenneth A., Sampson, Michael J.
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Editorial for the Special Issue on Flash Memory Devices. [PDF]
Micromachines (Basel), 2021 Zambelli C, Micheloni R.
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Controlling the Carrier Injection Efficiency in 3D Nanocrystalline Silicon Floating Gate Memory by Novel Design of Control Layer. [PDF]
Nanomaterials (Basel), 2023 Hu H +8 more
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Embedding security into ferroelectric FET array via in situ memory operation. [PDF]
Nat Commun, 2023 Xu Y +9 more
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Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories
ACM Transactions on Architecture and Code OptimizationWith the development of NAND flash memories’ bit density and stacking technologies, while storage capacity keeps increasing, the issue of reliability becomes increasingly prominent. Low-density parity check (LDPC) code, as a robust error-correcting code, is extensively employed in flash memory.
Qiao Li +9 more
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Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks. [PDF]
Nat Commun, 2023 Kim IJ, Kim MK, Lee JS.
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FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis. [PDF]
Micromachines (Basel), 2023 Gul W, Shams M, Al-Khalili D.
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CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory. [PDF]
Sci Adv, 2021 Kim MK, Kim IJ, Lee JS.
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