Results 1 to 10 of about 993 (140)
Time-Domain ADPLL BPSK, QPSK, and 8PSK Demodulators
Journal of Electrical and Computer EngineeringTime-domain all-digital-phase-locked-loop phase-shift-keying (PSK) demodulators are proposed for BPSK, QPSK, and 8PSK signals. The demodulator architectures are highly suitable for low-voltage nanoscale CMOS techology.
Phanumas Khumsat +3 more
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A Review on Micro-Watts All-Digital Frequency Synthesizers [PDF]
MicromachinesThis paper reviews recent developments in highly integrated all-digital frequency synthesizers suitable to deploy in low-power internet-of-things (IoT) applications.
Venkadasamy Navaneethan +4 more
doaj +2 more sources
An ADPLL-Based GFSK Modulator with Two-Point Modulation for IoT Applications [PDF]
SensorsTo establish ubiquitous and energy-efficient wireless sensor networks (WSNs), short-range Internet of Things (IoT) devices require Bluetooth low energy (BLE) technology, which functions at 2.4 GHz. This study presents a novel approach as follows: a fully
Nam-Seog Kim
doaj +2 more sources
Distributed clock generator for synchronous SoC using ADPLL network [PDF]
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013 International audienceThis paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs).
Akre, Jean-Michel +10 more
core +7 more sources
An analysis of ADPLL applications in various fields [PDF]
Indonesian Journal of Electrical Engineering and Computer Science, 2020 ADPLL is now an essential component in applications like wireless sensor networks, Internet of things, health care applications, agricultural applications, etc, and also due the requirement of digital implementation by the industries. ADPLL consists of a
Dinesh, R., Marimuthu, Ramalatha
core +5 more sources
Design of novel hybrid - digitally controlled oscillator for ADPLL
Memories - Materials, Devices, Circuits and Systems, 2023 Digitally Controlled Oscillators (DCOs) are an integral part of All Digital Phase Locked Loops (ADPLLs). It is used to generate output frequency corresponding to the applied digital input.
Mohd Ziauddin Jahangir +1 more
doaj +2 more sources
FPGA Implementation of ADPLL with Ripple Reduction Techniques [PDF]
International Journal of VLSI Design & Communication Systems, 2012 In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA.
Kusum Lata, Manoj Kumar
core +3 more sources
IEEE Access, 2021 This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications.
Muhammad Riaz Ur Rehman +14 more
doaj +1 more source
A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting
IEEE Access, 2021 This presents an all-digital phase-locked loop (ADPLL) system using triple-stage phase-shifting (TSPS) for fast locking. At the first stage, a phase-pulling multiplexer linearly pulls the phase of a feedback signal until the phase offset between the ...
Heon Hwa Cheong, Suhwan Kim
doaj +1 more source
FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter
SN Applied Sciences, 2022 This article describes about the design, implementation, and analysis of a true random number generator (TRNG) employing an all-digital phase-locked loop (ADPLL) based on a finite impulse response (FIR) filter as the digital loop filter and implemented ...
Huirem Bharat Meitei, Manoj Kumar
doaj +1 more source