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ALL Digital Phase-Locked Loop (ADPLL): A Survey

open access: yesInternational Journal of Future Computer and Communication, 2013
Kusum Lata, Manoj Kumar
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Comparison of various optimized architectures of DCO for ADPLL

open access: yesContemporary Engineering Sciences, 2014
B. Narendran, R. Parameshwaran
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Loop Latency Compensation Technique for Wide Loop Bandwidth ADPLL

open access: yesLoop Latency Compensation Technique for Wide Loop Bandwidth ADPLL
identifier:oai:t2r2.star.titech.ac.jp ...
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FPGA Validation of Event-Driven ADPLL

2020 European Conference on Circuit Theory and Design (ECCTD), 2020
In this paper, we perform FPGA modeling of an event-driven all-digital phase locked loop (ADPLL) with asynchronous control. We perform the comparison with a theoretical model through a transient response, phase plane representation, and the order parameter.
Eugene Koskin   +3 more
openaire   +1 more source

A Digitally Controlled Oscillator for ADPLL Application

Applied Mechanics and Materials, 2012
In order to solve the defects in performance for analog RF circuit in deep submicron process, this paper discusses a new type of LC oscillators(Digitally Controlled Oscillator), which uses digital RF method to achieve the technology requirements of wireless communication.
Xiu Long Wu   +3 more
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