Results 111 to 120 of about 993 (140)
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ADPLL design and implementation on FPGA
2013 International Conference on Intelligent Systems and Signal Processing (ISSP), 2013This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 10.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this paper, implementation of ADPLL is described in detail.
Kusum Lata, Manoj Kumar
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A glitch-corrector circuit for low-spur ADPLLs
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009), 2009This paper analyzes the effect of the time skew between counter and TDC inputs in the generation of spurious tones in the output spectrum of an All-Digital PLL (AD-PLL) and proposes a simple glitch-removal circuit, capable of operating even in the presence of fast and large frequency drifts. This technique is applied to the design of a 90-nm CMOS ADPLL
ZANUSO, MARCO +5 more
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A glitch-corrector circuit for low-spur ADPLLs
Analog Integrated Circuits and Signal Processing, 2011This paper analyzes the effect of the time skew between counter and TDC inputs in the generation of spurious tones in the output spectrum of an All-Digital PLL (AD-PLL) and proposes a simple glitch-removal circuit, capable of operating even in the presence of fast and large frequency drifts.
ZANUSO, MARCO +3 more
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A fractional frequency synthesizer based on ADPLL
2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672), 2004In this paper, we proposed a fractional frequency synthesizer based on all digital phase-locked loop (ADPLL). A new phase frequency acquisition mode is involved with an initial half-step size to speed up the convergence in phase and frequency comparisons.
null Chia-Chun Tsai +2 more
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Comparison of Two ADPLL Structures for IoT Applications
2019 International Conference on Recent Advances in Energy-efficient Computing and Communication (ICRAECC), 2019All digital Phase locked loop (ADPLL) based wireless transceiver is a key block in IoT based wireless communications. Locking time, power consumption and frequency resolution of ADPLL are the most important parameters to be considered in increasing the efficiency of IoT applications.
R. Dinesh, Ramalatha Marimuthu
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An ADPLL circuit using a DDPS for genlock applications
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004This paper presents a fully programmable All-Digital PLL (ADPLL) circuit that is able to synchronize any frequency between 12 MHz and 200 MHz, with a frequency between 24 Hz and 100 MHz. This ADPLL circuit uses a Direct Digital Period Synthesizer as a digitally controlled oscillator.
D.E. Calbaza +3 more
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ADPLL design parameters determinations through noise modeling
Integration, 2015This paper presents a methodology to determine all-digital phase-locked loop (ADPLL) circuit variables based on required design specifications, including output phase noise, fractional spur and locking time. An analytical model is developed to characterize the effects of different noise sources on ADPLL output phase noise and fractional spur.
Bo Jiang, Tian Xia
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Analytical Predictions of Phase Noise in ADPLLs
2013In this chapter, we will derive analytical predictions of the phase noise in TDC-based and accumulator-based ADPLLs with \(l\)th-order noise shaping TDCs and DCO driven by a sigma-delta modulator.
Francesco Brandonisio +1 more
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2020
To realize ULP fractional-N ADPLL with low jitter and low spurs, the first-order DSM-based fractional controller works in conjunction with a highly linear DTC. The rms jitter can be improved when compared to using higher-order DSM, and for this a DTC with high linearity is required.
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To realize ULP fractional-N ADPLL with low jitter and low spurs, the first-order DSM-based fractional controller works in conjunction with a highly linear DTC. The rms jitter can be improved when compared to using higher-order DSM, and for this a DTC with high linearity is required.
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A low power clock generator 400–1800 MHz for ADPLL
Journal of Instrumentation, 2022Abstract This paper describes a low-power all-digital clock generator (ADCG) designed for reading and processing signals from detectors of large physical experiments. The clock generator operates with a reference clock frequency of 10 to 50 MHz and generates an output signal ranging from 400 to 1800 MHz in 10 MHz steps.
E. Atkin, P. Ivanov, D. Normanov
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