Results 11 to 20 of about 993 (140)
An Interpolated Flying-Adder-Based Frequency Synthesizer
Journal of Electrical and Computer Engineering, 2011 This work presents an interpolated flying-adder- (FA-) based frequency synthesizer. The architecture of an interpolated FA, which uses an interpolated multiplexer (MUX) to replace the multiplexer in conventional flying adder, improves the cycle-to-cycle ...
Pao-Lung Chen, Chun-Chien Tsai
doaj +2 more sources
Parallel PWMs based fully digital transmitter with wide carrier frequency range. [PDF]
ScientificWorldJournal, 2013 The carrier‐frequency (CF) and intermediate‐frequency (IF) pulse‐width modulators (PWMs) based on delay lines are proposed, where baseband signals are conveyed by both positions and pulse widths or densities of the carrier clock. By combining IF‐PWM and precorrected CF‐PWM, a fully digital transmitter with unit‐delay autocalibration is implemented in ...
Zhou B, Zhang K, Zhou W, Zhang Y, Liu D.
europepmc +2 more sources
Design of a high‐performance advanced phase locked loop with high stability external loop filter
IET Circuits, Devices &Systems, Volume 17, Issue 1, Page 1-12, January 2023., 2023 Abstract For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase‐frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer
Kalpana Kasilingam +3 more
wiley +1 more source
A 190.3‐dBc/Hz FoM 16‐GHz rotary travelling‐wave oscillator with reliable direction control
Electronics Letters, Volume 57, Issue 5, Page 209-211, March 2021., 2021 Abstract This letter presents a rotary travelling‐wave oscillator (RTWO) with reliable direction control in a standard 130 nm complementary metal–oxide–semiconductor (CMOS) technology. To achieve low phase noise (PN), and low power consumption, 16‐stages customised transmission line segments are designed and simulated on electromagnetic tools.
Fangzhou Sun +3 more
wiley +1 more source
Mathematical Problems in Engineering, Volume 2021, Issue 1, 2021., 2021 This research proposed the design and calculations of ultra‐low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF‐nMOS subthreshold or triode region to achieve ultra‐
Muhammad Ovais Akhter +2 more
wiley +1 more source
FPGA Based Modelling of an ADPLL Network [PDF]
2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2019 This paper introduces and compares the implementation of a number of FPGA based ADPLL network prototyping architectures. Networks are then created using three different ADPLL implementations and tests performed on each. Based on these test results, comparison is made to both the expected performance and role of each ADPLL design as a development tool.
Dooley, C. +3 more
openaire +2 more sources
IEEE Access, 2021 An all-digital phase-locked loop (ADPLL) with a multiphase digitally controlled oscillator (DCO) incorporating the bootstrapped and interpolated schemes is proposed in this paper.
Jen-Chieh Liu, Yu-Ping Li
doaj +1 more source
Master‐Slave Topologies with Phase‐Locked Loops
Wireless Communications and Mobile Computing, Volume 2020, Issue 1, 2020., 2020 Since phase‐locked loops (PLLs) were conceived by Bellescize in 1932, their presence has become almost mandatory in any telecommunication device or network, being the essential element to recover frequency and phase information. As the technology developed, PLL appeared in several applications, such as, dense communication networks, smart grids ...
José Roberto C. Piqueira +1 more
wiley +1 more source
Design of a 3 GHz fine resolution LC DCO [PDF]
, 2017 In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning.
Zhao, Xuming, active 21st century
core +1 more source
Design of a compact and low-power TDC for an array of SiPM's in 110nm CIS technology [PDF]
, 2017 Silicon photomultipliers (SiPMs) are meant to substitute photomultiplier tubes in high-energy physics detectors and nuclear medicine. This is because of their -to name a few interesting properties- compactness, lower bias voltage, tolerance to magnetic ...
Bandi, Franco +3 more
core +1 more source