Results 21 to 30 of about 993 (140)
A Scalable DCO Design for Portable ADPLL Designs [PDF]
2005 IEEE International Symposium on Circuits and Systems, 2005 A novel digital controlled oscillator (DCO) design methodology is presented in this paper. The new design methodology includes a scalable DCO architecture and the developed design flow. With precise analysis in early stage, the design effort of DCO can be reduced significantly.
Wu, Chia-Tsun +3 more
openaire +2 more sources
Design and VHDL Modeling of All-Digital PLLs [PDF]
, 2010 International audienceIn this paper, a VHDL model of a second-order alldigital phase-locked loop (ADPLL) based on bang-bang phase detectors is presented.
Anceau, François +5 more
core +3 more sources
A Novel Architecture of ADPLL Using Cordic Algorithm for Low-Frequency Application [PDF]
, 2023 All Digital Phase Locked Loop (ADPLL) has many applications in digital communication. It is difficult for low-frequency applications to achieve the lock state quickly.
Velamarthi Spandana,, et al.
core +2 more sources
FPGA implementation of reconfigurable ADPLL network for distributed clock generation [PDF]
, 2011 International audienceThis paper presents an FPGA platform for the design and study of network of coupled All-Digital Phase Locked Loops (ADPLLs), destined for clock generation in large synchronous System on Chip (SoC).
Anceau, François +9 more
core +3 more sources
A clock network of distributed ADPLLs using an asymmetric comparison strategy [PDF]
, 2010 International audienceIn this paper, we describe an architecture of a distributed ADPLL (All Digital Phase Lock Loop) network based on bang-bang phase detectors that are interconnected asymmetrically.
Blanco, Eric +5 more
core +3 more sources
Dynamic Power Management for Neuromorphic Many-Core Systems [PDF]
, 2019 This work presents a dynamic power management architecture for neuromorphic many core systems such as SpiNNaker. A fast dynamic voltage and frequency scaling (DVFS) technique is presented which allows the processing elements (PE) to change their supply ...
Cederstroem, Love +14 more
core +2 more sources
A Low Power All-Digital PLL With −40dBc In-Band Fractional Spur Suppression for NB-IoT Applications
IEEE Access, 2019 This paper proposes a low-power fractional-N all-digital PLL (ADPLL) for the narrow-band Internet-of-Things applications. Multi-step lock controlling and oscillator tuning word coarse prediction algorithms help to accelerate the locking process to less ...
Na Yan +6 more
doaj +1 more source
A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class‐C DCO
Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018., 2018 This paper implements a complementary Class‐C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start‐up with low power consumption.
Lei Ma +5 more
wiley +1 more source
A Design Approach for Networks of Self-Sampled All-Digital Phase-Locked Loops [PDF]
, 2011 International audienceThis paper addresses the problem of the stability and the performance analysis of N-nodes Cartesian networks of self-sampled all digital phase-locked loops.
Akré, Jean-Michel +6 more
core +3 more sources
IEEE Access, 2020 In this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL) with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth low energy (BLE) transceiver in Internet-of-Things (IoT) is ...
Imran Ali +9 more
doaj +1 more source