Results 31 to 40 of about 993 (140)
A Robust and Efficient Fault-Resilient RadHard ADPLL
International Journal of Systems Applications, Engineering & Development, 2020 The high pace emergence in semiconductor technologies and associated application demands have revitalized industries to explore power efficient, stable and fault tolerant digital communication solutions, particularly for time critical applications operating at higher frequency ranges.
Varsha Prasad, Sandya Prasad
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A Low Power Impedance Transparent Receiver with Linearity Enhancement Technique for IoT Applications
Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018., 2018 A low power receiver with impedance transparent RF front end is presented. By using the 4‐path passive mixer and the active feedback of LNA, the baseband impedance profile is further transferred to receiver input. While a LO‐defined input matching is formed by RF front end, the linearity of entire receiver chain is improved.
Sizheng Chen +6 more
wiley +1 more source
Journal of Sensors, Volume 2017, Issue 1, 2017., 2017 A digital closed‐loop driving technique is presented in this paper that uses the PFD‐ (phase frequency detector‐) based CORDIC (coordinate rotation digital computer) algorithm for a biaxial resonant microaccelerometer. A conventional digital closed‐loop self‐oscillation system based on the CORDIC algorithm is implemented and simulated using Simulink ...
Bo Yang +4 more
wiley +1 more source
A Novel Fast-Locking ADPLL Based on Bisection Method [PDF]
Electronics, 2021 Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency ...
Xiaoying Deng +2 more
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CMOS time‐to‐digital converters for mixed‐mode signal processing
The Journal of Engineering, Volume 2014, Issue 4, Page 140-154, April 2014., 2014 This study provides an in‐depth review of the principles, architectures and design techniques of CMOS time‐to‐digital converters (TDCs). The classification of TDCs is introduced. It is followed by the examination of the parameters quantifying the performance of TDCs.
Fei Yuan
wiley +1 more source
Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL
IEEE AccessA new technique for generating true random numbers by using the ADPLL (All Digital Phase Locked Loop)-based multiple ring oscillator TRNG (MURO-TRNG) is discussed in this paper.
Huirem Bharat Meitei, Manoj Kumar
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Contributions to the analysis and design of an ADPLL [PDF]
2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006 In this paper, we propose two contributions to the simulation and design of an All-Digital Phase-Locked Loop (ADPLL) for RF applications. First, we extend the behavioral model we already proposed, in order to include detailed fractional aspects. Second, we propose a new adaptive algorithm that can be integrated in this ADPLL in order to lower its ...
Cyril Joubert +4 more
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International Journal of Reconfigurable Computing, Volume 2014, Issue 1, 2014., 2014 This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL combines classic closed‐loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum likelihood frequency estimator (MLFE) so as to make the best use of the advantages of the two types ...
Kaiyu Wang +5 more
wiley +1 more source
Control law synthesis for distributed multi-agent systems: Application to active clock distribution networks [PDF]
, 2011 International audienceIn this paper, the problem of active clock distribution network synchronization is considered. The network is made of identical oscillators interconnected through a distributed array of phase-locked-loops (PLLs).
Blanco, Eric +5 more
core +4 more sources
A Concept of Synchronous ADPLL Networks in Application to Small-Scale Antenna Arrays
IEEE Access, 2018 In this paper, we introduce a reconfigurable oscillatory network that generates a synchronous and distributed clocking signal. We propose an accurate model of the network to facilitate the study of its design space and ensure that it operates in its ...
Eugene Koskin +2 more
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