Results 41 to 50 of about 993 (140)
, 2015 Precision phase readout of optical beat note signals is one of the core techniques required for intersatellite laser interferometry. Future space based gravitational wave detectors like eLISA require such a readout over a wide range of MHz frequencies ...
Anders Enggaard +21 more
core +1 more source
Noise shaping Asynchronous SAR ADC based time to digital converter [PDF]
, 2018 Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits.
Katragadda, Sowmya
core +1 more source
480 MHz 10‐tap Clock Generator Using Edge‐Combiner DLL for USB 2.0 Applications
Journal of Electrical and Computer Engineering, Volume 2012, Issue 1, 2012., 2012 A clock generator with an edge‐combiner DLL (ECDLL) has been developed for USB 2.0 applications. The clock generator generates 480 MHz 10‐tap output signals from a 12 MHz reference signal and consists of three DLLs to shrink the design area so that it is smaller than a conventional one based on a PLL.
Takashi Kawamoto +3 more
wiley +1 more source
IEEE AccessThis paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho +9 more
doaj +1 more source
Design of Digital Frequency Synthesizer for 5G SDR Systems [PDF]
, 2022 The previous frequency synthesizer techniques for scalable SDR are not compatible with high end applications due to its complex computations and the intolerance over increased path interference rate which leads to an unsatisfied performance with improved
Bhaskar C., Vijaya, P. Munaswamy
core +2 more sources
Design of an All‐Digital Synchronized Frequency Multiplier Based on a Dual‐Loop (D/FLL) Architecture
VLSI Design, Volume 2012, Issue 1, 2012., 2012 This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all‐digital dual‐loop delay‐ and frequency‐locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA ...
Maher Assaad +2 more
wiley +1 more source
A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL
IEEE AccessThe phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this
Haoyang Shen +4 more
doaj +1 more source
, 2013 Inter satellite laser interferometry is a central component of future space-borne gravity instruments like LISA, eLISA, NGO and future geodesy missions.
Bykov, Iouri +6 more
core +1 more source
Synchronized State in Networks of Digital Phase-Locked Loops [PDF]
, 2010 International audienceClock distribution networks of synchronized oscillators are an alternative approach to classical tree-like clock distribution methods.
Akre, Jean-Michel +3 more
core +3 more sources
Cognitive Radio RF: Overview and Challenges
VLSI Design, Volume 2012, Issue 1, 2012., 2012 Cognitive radio system (CRS) is a radio system which is aware of its operational and geographical environment, established policies, and its internal state. It is able to dynamically and autonomously adapt its operational parameters and protocols and to learn from its previous experience.
Van Tam Nguyen +3 more
wiley +1 more source