Results 51 to 60 of about 993 (140)

RF Front‐End Circuits and Architectures for IoT/LTE‐A/5G Connectivity

, 2018
Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018.
Yan Li, Donald Y. C. Lie, Chaojiang Li, Dixian Zhao, Christian Fager   +4 more
wiley   +1 more source

Semidigital PLL Design for Low‐Cost Low‐Power Clock Generation

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
This paper describes recent semidigital architectures of the phase‐locked loop (PLL) systems for low‐cost low‐power clock generation. With the absence of the time‐to‐digital converter (TDC), the semi‐digital PLL (SDPLL) enables low‐power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology ...
Ni Xu, Woogeun Rhee, Zhihua Wang, Sudhakar Pamarti   +3 more
wiley   +1 more source

Performance evaluation of the time delay digital tanlock loop architectures [PDF]

, 2015
This article presents the architectures, theoretical analyses and testing results of modified time delay digital tanlock loop (TDTLs) system. The modifications to the original TDTL architecture were introduced to overcome some of the limitations of the ...
Al-Kharji Al-Ali O., Al-Kharji Al-Ali O., Anani N., Best R. E., Crawford J. A., Haykin S., Mahmoud Al-Qutayri, Nader Anani, Omar Al-Kharji Al-Ali, Peeblesand P. Z., Prasad Ponnapalli, Saleh Al-Araji   +11 more
core   +1 more source

Open‐Loop Wide‐Bandwidth Phase Modulation Techniques

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
The ever‐increasing growth in the bandwidth of wireless communication channels requires the transmitter to be wide‐bandwidth and power‐efficient. Polar and outphasing transmitter topologies are two promising candidates for such applications, in future. Both these architectures require a wide‐bandwidth phase modulator.
Nitin Nidhi, Pin-En Su, Sudhakar Pamarti, Kenichi Okada   +3 more
wiley   +1 more source

Phase Locked-Loop Design of High-Order Automotive Frequency Modulated Continuous Wave Radar Based on Fast Integration Structure

IEEE Access
In recent years, frequency-modulated continuous-wave (FMCW) radars have been widely used in the automotive field to measure the relative distance and speed of external targets.
Mengwei Yang, Jinyou Chen, Changhong Shan   +2 more
doaj   +1 more source

Relationship between Jitter variance, Lock time and Phase noise of a second-order PLL. [PDF]

, 2019
This paper covers analytical relationships between phase noise, lock time and jitter variance. An expression is derived for Lock time in terms phase margin.
Kadambi, Govind, Mazumdar, Dipayan, Vershinin, Yuri   +2 more
core   +1 more source

A Low‐Power Digitally Controlled Oscillator for All Digital Phase‐Locked Loops

VLSI Design, Volume 2010, Issue 1, 2010., 2010
A low‐power and low‐jitter 12‐bit CMOS digitally controlled oscillator (DCO) design is presented. The Low‐Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters.
Jun Zhao, Yong-Bin Kim, Gregory D. Peterson   +2 more
wiley   +1 more source

Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques

IEEE Open Journal of the Solid-State Circuits Society
This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power ...
Teerachot Siriburanon, Chunxiao Liu, Jianglin Du, Robert Bogdan Staszewski   +3 more
doaj   +1 more source

Design and Implementation of FPGA based linear All Digital Phase-Locked Loop for Signal Processing Applications [PDF]

, 2012
This project presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the ...
Das, Abhishek, Dash, Suraj
core  

Verification in ACL2 of a Generic Framework to Synthesize SAT–Provers [PDF]

, 2002
We present in this paper an application of the ACL2 system to reason about propositional satisfiability provers. For that purpose, we present a framework where we define a generic transformation based SAT–prover, and we show how this generic framework
Alonso Jiménez, José Antonio, Hidalgo Doblado, María José, Martín Mateos, Francisco Jesús, Ruiz Reina, José Luis   +3 more
core   +1 more source