Results 61 to 70 of about 993 (140)
A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL
IEEE Open Journal of the Solid-State Circuits SocietyThis article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF ...
Linsheng Zhang +9 more
doaj +1 more source
Synchronization of Coupled Boolean Phase Oscillators
, 2014 We design, characterize, and couple Boolean phase oscillators that include state-dependent feedback delay. The state-dependent delay allows us to realize an adjustable coupling strength, even though only Boolean signals are exchanged.
Gauthier, Daniel J. +2 more
core +3 more sources
Research on ADPLL for High-Precision Phase Measurement
SymmetryThe inter-satellite laser interferometer, which functions as a high-performance displacement sensor, will be used in forthcoming space-based gravitational wave detection missions. The readout of these interferometers is typically performed by phasemeters based on all-digital phase-locked loops (ADPLLs) implemented in FPGAs.
Weilai Yao +3 more
openaire +1 more source
A High-Performance Time-to-Digital Converter in QCA Technology Employing a Low-Power D Flip-Flop
IEEE AccessThis paper presents a low-power and compact Time-to-Digital Converter (TDC) implemented using Quantum-dot Cellular Automata (QCA) technology. The proposed architecture extends our previous QCA-based TDC design by incorporating a multiplexer-based D-latch
Shahram Modanlou, Mohammad Gholami
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전원 잡음에 둔감한 고리 발진기와 디지털 위상 동기 회로 설계 [PDF]
, 2023 학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 2. 정덕균.One of the critical blocks integrated into the PAM4-binary bridge, bridging the high-speed DRAM and the low-speed DRAM Tester, is an All-Digital Phase-Locked Loop (ADPLL).
백경민
core
Guangtongxin yanjiu, 2006 文章首先介绍了全数字锁相环（ADPLL）的基本结构和工作原理,并进行了数学建模,计算了其主要的参数指标;然后,针对SDH设备时钟（SEC）设计了一种切实可行的低抖动ADPLL的电路结构,并对其各个组成部分进行了具体的电路分析和设计,通过微机适当配置,可以使该设计的结果得到优化;最后,通过现场可编程门阵列（FPGA）验证,给出了测试结果。
张继勇, 王爱国
doaj
Digital controlled oscillator (DCO) for all digital phase-locked loop (ADPLL) – a review [PDF]
, 2019 Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS)
Badal, Md Torikul Islam +6 more
core +2 more sources
비례 이득값과 적분 이득값의 동시 최적화 기술을 사용하는 ADPLL의 설계 [PDF]
, 2023 학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 8. 정덕균.Noise performance of a PLL is an important factor to consider when designing a PLL. The unwanted variation in the timing clock edges can deteriorate system performance.
하경준
core
Digital Phase-Locked Loops: Exploring Different Boundaries
IEEE Open Journal of the Solid-State Circuits SocietyThis article examines the research area of digital phase-locked loops (DPLLs), a critical component in modern electronic systems, from wireless communication devices to RADAR systems and digital processors. As the demands for higher integration levels in
Yuncheng Zhang +2 more
doaj +1 more source
Exploring the Landscape of Phase-Locked Loop Architectures: A Comprehensive Review
IEEE AccessThis paper aims to explore diverse landscape of Phase Locked Loops (PLLs), offering a comprehensive categorization and in-depth analysis of their underlying working principles.
Debojyoti Dutta +3 more
doaj +1 more source