Results 71 to 80 of about 993 (140)

Digital command system second-order subcarrier tracking performance [PDF]

Equations to determine tracking performance for second order, phase locked loop used for subcarrier synchronization on digital command ...
Holmes, J. K., Tegnelia, C. R.
core   +1 more source

The Design of DDS ADPLL using ARM Micro Controller

International Journal for Research in Applied Science and Engineering Technology, 2022
Abstract: Abstract In this article, a full custom design and implementation of a sine wave All Digital Phase Lock Loop (ADPLL) system based on ARM microcontroller is described. These ADPLL implementations are also referred as Software - Direct Digital Synthesis ADPLL (DDS-ADPLL).
openaire   +1 more source

Designing a time-to-digital converter using quantum-dot cellular automata nanotechnology

Scientific Reports
As a nanoscale computing paradigm, quantum-dot cellular automata (QCA) technology demonstrates significant advantages over conventional CMOS implementations, including improved device density, minimized power dissipation, and increased operational speed.
Shahram Modanlou, Mohammad Gholami
doaj   +1 more source

Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation

IEEE Open Journal of the Solid-State Circuits Society
A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7).
Yizhe Hu, Weichen Tao, Robert Bogdan Staszewski   +2 more
doaj   +1 more source

Linearity Calibration Method for Stochastic Time-to-Digital Converters

IEEE Access
Stochastic Time-to-Digital Converters (STDCs) can theoretically achieve very fine time resolutions utilizing random time offsets caused by device mismatch rather than relying on delay elements.
Woongdae Na, Hayun Chung
doaj   +1 more source

An Analog Phase Interpolation Based Fractional-N PLL [PDF]

, 2016
A novel phase-locked loop topology is presented. Compared to conventional designs, this architecture aims to increase frequency resolution and reduce quantization noise while maintaining the fractional-N benefits of high bandwidth and low phase noise up-
Bluestone, Aaron James
core   +1 more source

Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation. [PDF]

Sensors (Basel), 2021
Sheng D, Chen WY, Huang HT, Tai L.
europepmc   +1 more source

Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing. [PDF]

Sensors (Basel), 2022
Lai WC.
europepmc   +1 more source

A Robust and Efficient Fault-Resilient Rad Hard ADPLL

International Journal of Engineering and Advanced Technology, 2019
Typically, classical PLLs adopt analog design methods. However integrating PLL with noise-prone application environment is highly tedious and somewhere confined. As per current knowledge majority of PLLs apply Analog Loop Filters (ALFs) and Voltage Controlled Oscillators which are practically highly complicated to integrate with noisy environment. Even
Varsha Prasad*, Dr S Sandya
openaire   +1 more source

La représentation du verbe dans les manuels de français pour le primaire [PDF]

, 2005
Le verbe est une unité problématique pour les manuels. Il ne présente pas la même saillance lexicale que le nom, du fait notamment qu'il se conjugue et admet des compléments1. Ces propriétés le rangent préférentiellement du côté de la grammaire.
Petit, Gérard
core   +2 more sources