Results 81 to 90 of about 993 (140)
Design of a digitally controlled ring oscillator for ADPLL
, 2022 Sayısal olarak kontrol edilen osilatör, özellikle PLL'lerde geniş kullanımları nedeniyle yaygın olarak araştırılan bir devredir. Bu tez, yeterince geniş bir ayar aralığına ve ince frekans adımlarına sahip, sayısal olarak kontrol edilen bir halka osilatörü önermektedir.
openaire +1 more source
, 2013 National audienceLe thème de ce papier concerne la comparaison d'architectures numériques pour l'annulation de plusieurs spurs, pollutions internes qui surviennent dans les terminaux Radio fréquence (RF).
Belvèze, Fabrice +3 more
core
Digital Phase Locked-Loop With Wide Tuning Range And Dynamic Phase Shift [PDF]
, 2014 For decades, Phase Lock Loop (PLL) has been widely used in numerous systems, such as telecommunications and digital design, where it plays significant role in improving overall system timing.
Rosle, Anafaezalena
core
Design, Analysis and Implementation of DLL clock generator [PDF]
In this paper we present design, analysis and implementation of Delay Locked Loop (DLL) based clock generator circuits. In this work a DLL has been proposed the design uses dynamic phase detector (PD) for phase detection.
Anupama, Ms., Changlani, Dr. Soni
core +1 more source
Resonant frequency tracking mode on eddy current pulsed thermography non-destructive testing. [PDF]
Philos Trans A Math Phys Eng Sci, 2020 Miao L, Gao B, Li H, Tian G.
europepmc +1 more source
An Effective Low Power Ring Oscillator Based All Digital Phase Locked Loop [PDF]
, 2019 The All digital phase-locked loops (ADPLL) widely employed in the data communication systems including, but not limited to, the implementation of the frequency multiplication and clock synchronization circuits.
Jeslin Jijo , J., R. Dinesh , Mr.
core +1 more source
NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. [PDF]
Sensors (Basel), 2020 Borejko T +11 more
europepmc +1 more source
[[alternative]]Filter Design of Phase-Locked Loops [PDF]
計畫編號：NSC90-2213-E032-008研究期間：200108~200207研究經費：307,000[[sponsorship ...
周永山
core
A Bang-Bang All-Digital PLL for Frequency Synthesis [PDF]
, 2012 : Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF ...
core
A Wide-Band Digital Lock-In Amplifier and Its Application in Microfluidic Impedance Measurement. [PDF]
Sensors (Basel), 2019 Huang K +7 more
europepmc +1 more source