Results 281 to 290 of about 6,822 (302)
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An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016With increased levels of integration in modern system-on-chips, the coupling of supply noise in a phase-locked loop (PLL) has become the dominant source of performance degradation in many systems. In this paper, an all-digital approach to canceling the effects of supply noise is presented.
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A novel Time-to-Digital Converter for All Digital Phase-Locked Loop
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2018This paper presents a new design of a two-step Time-to-Digital Converter (TDC), which reduces the complexity of the circuits, and the power consumption and area of the circuit. The on-line self-calibration method for the time amplifier (TA) without any other calibration circuits is proposed to solve the nonlinearity of the TA.
GAI Lin-chong, CHEN Lan, WANG Hai-yong
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Implementation Of An Efficient All Digital Phase Locked Loop
2022 2nd Asian Conference on Innovation in Technology (ASIANCON), 2022Haritha Krishnan, Rajeswari P
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A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm
IEEE Transactions on Circuits and Systems II: Express Briefs, 2011Shen-Iuan Liu
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Noise-Shaping All-Digital Phase-Locked Loops
2014Francesco Brandonisio +1 more
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Chaos and bifurcation in a third-order digital phase-locked loop
AEU - International Journal of Electronics and Communications, 2008Tanmoy Banerjee, Bishnu Charan Sarkar
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A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function
IEEE Journal of Solid-State Circuits, 2014Sigang Ryu, Yoontaek Lee, Seuk Son
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