Results 271 to 280 of about 6,822 (302)
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All Digital Phase-Locked Loops
1998In this chapter, we are going to extend our survey to loops that have do not have analog prototypes. Lindsey and Chie [1] performed a 1981 survey of digital PLLs that is recommended to the reader desiring additional architectures.
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Novel Fractional Spur Relocation in All Digital Phase Locked Loops
2017 IEEE Wireless Communications and Networking Conference (WCNC), 2017We present a new model that estimates the locations of the fractional spurs relative to the center carrier. Based on this model, we present a novel technique to mitigate the effect of fractional spurs generated in All-Digital Phase Locked Loops. Instead of using power-consuming spur cancellation algorithms, the proposed scheme enables to move the ...
Basak Can +3 more
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Adaptive Spur Cancellation Technique in All-Digital Phase-Locked Loops
IEEE Transactions on Circuits and Systems II: Express Briefs, 2017The phenomenon of periodic phase errors (also known as spurs) in phase-locked loops (PLLs) is widely acknowledged and is responsible for posing considerable challenge on development of miniaturized wireless communication devices. The common approach employed today for spur mitigation calls for a digital notch filter within the receive chain, while ...
Rotem Avivi +6 more
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An overall gain estimation algorithm for all digital phase locked loops
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014Fully digital frequency synthesizers are increasingly used in radio frequency (RF) transceivers. The estimation and calibration of the gain for digital controlled oscillator (DCO) and time-to-digital converter (TDC) which is subject to process, voltage and temperature (PVT) variations are important area of research since they can increase the ...
Jing Li 0063 +5 more
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Full-custom all-digital phase locked loop for clock generation
VLSI Design, Automation and Test(VLSI-DAT), 2015A novel approach of constructing an All-Digital Phase Locked Loop (ADPLL) is presented in this paper. A 3-Step symmetric Time-to-Digital Converter (TDC) is proposed with both long dynamic range and high resolution. The Upper-and-Lower-boundaries-Cut-off-Determination (ULCD) logic is presented for a full-custom digital loop filter.
Mu-lee Huang, Chung-Chih Hung
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An all-digital phase-locked loop with a multi-delay-switching TDC
2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2017This paper presents a low-power time-to-digital converter (TDC) with multi-delay-switching mechanism for ADPLL application. In order to achieve low power dissipation and low area occupation, a switching mechanism is proposed on TDC design. The proposed ADPLL achieves the frequency range from 150 MHz to 1.45 GHz and 18.4 ps peak-to-peak jitter at 800 ...
Chung-Cheng Su +2 more
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0.5V 160-MHz 260uW all digital phase-locked loop
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2009A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with
Jen-Chieh Liu +3 more
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On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios
2007 IEEE 18th International Symposium on Personal, Indoor and Mobile Radio Communications, 2007A new all-digital phase-locked loop (ADPLL) for wireless applications has recently been proposed and commercially demonstrated. It replaces conventional phase/frequency detector and charge pump with a time-to-digital converter (TDC). Analog frequency tuning of a VCO is replaced with an all- digital tuning of a digitally-controlled oscillator (DCO). Due
Ioannis L. Syllaios +2 more
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Direct digital synthesis-based all-digital phase-locked loop
2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, 2009In this paper, we present an architecture for a PLL that is based on DDS and that can be implemented using all-digital components. The local oscillator is based on a DDS that is clocked by a local oscillator and that is synchronized to a crystal reference using a negative feedback which is similar to a PLL.
Benoit Vezant +3 more
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A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015A fast-locking all-digital phase-locked loop (ADPLL) including a fast-locking unit, a multi-level bang-bang phase detector (ML-BBPD), a dynamic gain adjustment controller (DGAC), and a digitally controlled oscillator (DCO) is presented. The ML-BBPD provides multi-level outputs with different phase errors.
Jung-Mao Lin, Ching-Yuan Yang
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