Results 261 to 270 of about 6,822 (302)

An FPGA-Based Linear All-Digital Phase-Locked Loop

IEEE Transactions on Circuits and Systems I: Regular Papers, 2010
In this paper, an all-digital phase-locked loop (ADPLL) is presented, and it is implemented on a field-programmable gate array. All components like the phase detector (PD), oscillator, and loop filter are realized as digital discrete-time components fed from analog-to-digital converters.
Martin Kumm, Harald Klingbeil, Peter Zipf   +2 more
openaire   +1 more source

CMOS High-Resolution All-Digital Phase-Locked Loop

2003 46th Midwest Symposium on Circuits and Systems, 2006
The core of an all-digital phase locked-loop (ADPLL) is composed of a high resolution digital controlled oscillator (DCO) circuit operating in a wide frequency range, a phase-frequency detector (PFD) and an up/down binary counter. The ADPLL can be reused in many system-on-chip (SoC) applications by a proper setting of the DCO and the PFD.
E. Mokhtari, M. Sawan
openaire   +2 more sources

A 2.4-GHz Low-Power All-Digital Phase-Locked Loop

IEEE Journal of Solid-State Circuits, 2009
This paper presents an all-digital phase-locked loop (ADPLL) for the 2.4-GHz ISM band frequency synthesis. The ADPLL is built around a digitally controlled LC oscillator. In the feedback path, a high-speed topology is employed for the variable phase accumulator to count full cycles of the RF output. A simple technique based on a short delay line in the
Xu, Liangge, Lindfors, Saska, Stadius, Kari, Ryynänen, Jussi   +4 more
openaire   +2 more sources

Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model

IEEE Transactions on Circuits and Systems II: Express Briefs, 2021
In this brief, we study jitter behavior in an event-driven self-sampled model of an All-Digital Phase-Locked Loop. We provide its steady-state analysis using simulations of a discrete-time model. We show that digital jitter, a function of two control parameters of the model, can be mapped onto a on-dimensional manifold and approximated via a simple ...
Koskin, Eugene, Bisiaux, Pierre, Galayko, Dimitri, Blokhina, Elena   +3 more
openaire   +2 more sources

Research and Application of All Digital Phase-Locked Loop

2009 Second International Conference on Intelligent Networks and Intelligent Systems, 2009
The structure of an all digital phase-locked loop technology, ADPLL, is proposed in this paper. And the digital phase detector, digital filter loops and digital-controlled oscillators are gradually analyzed. The time order graphs of all modules are presented.
Qiang Zhang, Kai Huang, Zuojun Liu, Zhigang Li   +3 more
openaire   +1 more source

The design of an all digital phase-locked loop

38th IEEE Vehicular Technology Conference, 2003
A method for synthesizing an all digital phase-locked loop is proposed. The design is based on the digitization of a continuous system whereby the s-plane poles and zeros of a specified differential equation are mapped to the z-plane poles and zeros of a corresponding difference equation using the matched z-transform method. The critical parameters are
openaire   +1 more source

All-digital phase locked loop design assistant

2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015
An All-Digital Integer-N Phase Locked Loop (ADPLL) design assistant that models all the sub-blocks and noise sources in phase domain has been developed. For chosen top level design parameters, the generator designs the desired closed loop, open loop and digital loop filter characteristics of the ADPLL and analyzes the resulting phase noise performance ...
Yalcin Balcioglu, Gunhan Dundar
openaire   +1 more source

A Simulink Model for All-Digital-Phase-Locked-Loop

2007 IEEE International Workshop on Radio-Frequency Integration Technology, 2007
A Simulink model for all-digital-phase-locked-look (ADPLL) is proposed in this paper. The study is based on ADPLL implemented in an all-digital RF transceiver. Simulation results in Simulink give the performance overview of the ADPLL.
Xiaoyan Wang, Yeung Bun Choi, Mingkyu Je, Wooi Gan Yeoh   +3 more
openaire   +1 more source

An all-digital phase-locked loop for digital power management integrated chips

2009 IEEE International Symposium on Circuits and Systems, 2009
An all-digital phase-locked loop (ADPLL) for digital power management applications is presented. The conventional RC loop filter is replaced by a digital loop filter, and the conventional analog voltage-controlled oscillator (VCO) is replaced by a digitally controlled oscillator (DCO).
Yu-Ming Chung, Chia-Ling Wei
openaire   +1 more source

Built-in Self-Test Circuits for All-digital Phase-Locked Loops

2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2019
This paper presents the design of an all-digital built-in self-test (BIST) circuit for all-digital phase-locked loops (ADPLLs). It measures clock jitter of the ADPLL and tests the PLL function blocks. The BIST circuit does not break the PLL loop. The jitter measurement circuit takes a frequency divider as a timing amplifier to linearly enlarge the ...
Ching-Che Chung, Wei-Jung Chu, Yi-Ting Tsai   +2 more
openaire   +1 more source