Results 81 to 90 of about 84,601 (236)

Design and Simulation of Low Power Consuming Digital Controlled Oscillator in All Digital Phase Locked Loop

International Journal of Innovative Technology and Exploring Engineering, 2019
Recent IC technology innovations can achieve lowpowe r biomedical implant functionality.RF transceivers require low-power and small-sized components in biomedical implants to achieve the best results in frequency and phase control. Phase Locked Loop (PLL)

semanticscholar   +1 more source

An ADPLL-Based GFSK Modulator with Two-Point Modulation for IoT Applications

Sensors
To establish ubiquitous and energy-efficient wireless sensor networks (WSNs), short-range Internet of Things (IoT) devices require Bluetooth low energy (BLE) technology, which functions at 2.4 GHz. This study presents a novel approach as follows: a fully
Nam-Seog Kim
doaj   +1 more source

A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process

IEEE Access
This paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun-Seong Kim, Yun-Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh   +9 more
doaj   +1 more source

Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation

IEEE Open Journal of the Solid-State Circuits Society
A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7).
Yizhe Hu, Weichen Tao, Robert Bogdan Staszewski   +2 more
doaj   +1 more source

Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL

IEEE Access
A new technique for generating true random numbers by using the ADPLL (All Digital Phase Locked Loop)-based multiple ring oscillator TRNG (MURO-TRNG) is discussed in this paper.
Huirem Bharat Meitei, Manoj Kumar
doaj   +1 more source

A 400 MHz 500-fs-Jitter Open-Loop DLL-Based Multi-Phase Clock Generator Utilizing an Noise-Free All-Digital Locking Detection Circuitry [PDF]

[[abstract]]An open-loop DLL-based multi-phase clock generator for low jitter applications is designed in 0.13µm CMOS technology. A noise-free all-digital locking detection circuitry (AD-LDC) is designed to detect whether the DLL is locked in time ...
Shih, Horng-Yuan
core  

Cascaded multiplexed optical link on a telecommunication network for frequency dissemination

, 2010
We demonstrate a cascaded optical link for ultrastable frequency dissemination comprised of two compensated links of 150 km and a repeater station.
Adil Haboucha, Anne Amy-Klein, Bruno Chanteau, Calhoun, Christian Chardonnet, Daussy, Fabien Kéfélian, Flambaum, Foreman, Fujieda, Giorgio Santarelli, Grosche, Haifeng Jiang, Jiang, Karshenboim, Kumagai, Kéfélian, Kéfélian, Lopez, Lopez, Musha, Newbury, Olivier Lopez, Schnatz, Shelkovnikov, Terra, Terra, Uzan, Vincent Roncin, Wilcox, Williams   +30 more
core   +2 more sources

Design of a High-Performance High-Pass Generalized Integrator Based Single-Phase PLL

, 2016
Grid-interactive power converters are normally synchronized to the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations and dc offsets
John, Vinod, Kulkarni, Abhijit
core   +1 more source

Linearity Calibration Method for Stochastic Time-to-Digital Converters

IEEE Access
Stochastic Time-to-Digital Converters (STDCs) can theoretically achieve very fine time resolutions utilizing random time offsets caused by device mismatch rather than relying on delay elements.
Woongdae Na, Hayun Chung
doaj   +1 more source

Sub-Threshold All-Digital DLL for Clock Generation of SAR ADC

IEEE Open Journal of Circuits and Systems
This paper presents a sub-threshold all-digital delay-locked loop (DLL) for the generation of the timing signals of low-power low-data-rate successive approximation register analog-to-digital converters.
Wenhao Wu, Fei Yuan, Yushi Zhou
doaj   +1 more source