Results 11 to 20 of about 4,121 (265)
Dual‐channel pre‐regulator structure for the bandgaps in high step‐down DC‐DC converters
Electronics Letters, 2023 High step‐down DC‐DC converters require a robust and low power pre‐regulated supply for bandgap reference. This paper proposes a structure that comprised of two current paths to achieve energy efficient pre‐regulation under high and low input voltage ...
Jiarui Ren, Yue Zhao, Zhiming Xiao
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Electronics Letters, 2023 In this letter, a new rail‐to‐rail two‐stage regenerative comparator for low supply voltage applications is presented. A rail‐to‐rail operation is achieved by utilizing an inverse inverter pre‐amplifier.
Hadi Pahlavanzadeh +2 more
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Electronics Letters, 2023 The fully passive noise shaping (NS) successive approximation register (SAR) analog‐to‐digital converters (ADCs) are simple, operational transconductance amplifier (OTA) free and scaling friendly. Previous passive NS‐SAR ADCs rely on the multi‐path‐input
Xingshuai Zou, Jiaxin Liu, Qiang Li
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Sensors, 2014 It is difficult for structural over-complete dictionaries such as the Gabor function and discriminative over-complete dictionary, which are learned offline and classified manually, to represent natural images with the goal of ideal sparseness and to ...
Zheng-Zhou Li +7 more
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Electronics Letters, 2023 A three‐stage rail‐to‐rail bulk‐driven class AB OTA that operates with ±0.15 V supplies and a power dissipation of 90 nW is introduced. The first two stages use resistive local common mode feedback. The OTA uses simple phase lead compensation.
Manaswini Gangineni +6 more
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Design and modelling of operational amplifier for energy systems [PDF]
E3S Web of Conferences, 2023 In the present study the single channel operational amplifier IS-OU1 with 15 V supply voltage (open loop gain ~100-110 dB) design is based on n-p-n type bipolar transistors has been developed.
Rybalka Sergey +2 more
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Asynchronous SAR ADC with self‐timed track‐and‐hold
Electronics Letters, 2023 This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in ...
Sunghyun Bae +4 more
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Advances in Condensed Matter Physics, 2015 In order to achieve a high breakdown voltage (BV) for the SOI (Silicon-On-Insulator) power device in high voltage ICs, a novel high voltage n-channel lateral double-diffused MOS (LDMOS) with a lateral variable interface doping profile (LVID) placed at ...
Jingjing Jin +7 more
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Systematic Design of a Pseudodifferential VCO Using Monomial Fitting
Elektronika ir Elektrotechnika, 2023 Digital integrated electronics benefits from its higher abstraction level, allowing optimisation methods and automated workflows. However, analogue integrated circuit design is still predominantly done manually, leading to lengthy design cycles.
Nicolai J. Dahl +2 more
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Low‐leakage zero‐static power consumption analogue CMOS switch
Electronics Letters, 2021 The architecture of a low‐leakage switch in complementary metal‐oxide‐semiconductor (CMOS) technology developed to implement long‐term analogue memories for low‐power applications is presented.
Giuseppe Sciortino +4 more
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