Results 21 to 30 of about 3,221,776 (178)
A three‐stage rail‐to‐rail bulk‐driven class AB OTA that operates with ±0.15 V supplies and a power dissipation of 90 nW is introduced. The first two stages use resistive local common mode feedback. The OTA uses simple phase lead compensation.
Manaswini Gangineni +6 more
doaj +1 more source
Design and modelling of operational amplifier for energy systems [PDF]
In the present study the single channel operational amplifier IS-OU1 with 15 V supply voltage (open loop gain ~100-110 dB) design is based on n-p-n type bipolar transistors has been developed.
Rybalka Sergey +2 more
doaj +1 more source
Asynchronous SAR ADC with self‐timed track‐and‐hold
This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in ...
Sunghyun Bae +4 more
doaj +1 more source
In order to achieve a high breakdown voltage (BV) for the SOI (Silicon-On-Insulator) power device in high voltage ICs, a novel high voltage n-channel lateral double-diffused MOS (LDMOS) with a lateral variable interface doping profile (LVID) placed at ...
Jingjing Jin +7 more
doaj +1 more source
Systematic Design of a Pseudodifferential VCO Using Monomial Fitting
Digital integrated electronics benefits from its higher abstraction level, allowing optimisation methods and automated workflows. However, analogue integrated circuit design is still predominantly done manually, leading to lengthy design cycles.
Nicolai J. Dahl +2 more
doaj +1 more source
Built-in-self-test of analogue circuits using optimised fault sets and transient response testing [PDF]
Transient Response Testing has been shown to be a very powerful and economical functional test technique for linear analogue cells in mixed-signal systems.
Axelos, N. +7 more
core +1 more source
Low‐leakage zero‐static power consumption analogue CMOS switch
The architecture of a low‐leakage switch in complementary metal‐oxide‐semiconductor (CMOS) technology developed to implement long‐term analogue memories for low‐power applications is presented.
Giuseppe Sciortino +4 more
doaj +1 more source
A neural network based background calibration for pipelined‐SAR ADCs at low hardware cost
This paper proposes a background calibration scheme for the pipelined‐Successive Approximation Register (SAR) Analog‐to‐Digital Converter (ADC) based on the neural network.
Yuguo Xiang +5 more
doaj +1 more source
This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of ...
Jaehyuk Lee +9 more
doaj +1 more source
Programmable mixed-signal circuits
A novel concept for programmable mixed-signal circuits is presented based on programmable transmission gates. For implementation, memristively switching devices are suggested as the most promising candidates for realization of fast and small-footprint ...
S. Tappertzhofen
doaj +1 more source

