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Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory

IEEE Journal of the Electron Devices Society
In this paper, we propose a low-power stack-level programming scheme for ultrahigh stack 3D NAND flash memory. As the number of word lines (WLs) increases beyond 300 layers, the increased pass voltage leads to excessive power consumption and reliability ...
Kyungmin Lee +3 more
doaj +1 more source

Surface-Potential-Based Drain Current Model of Gate-All-Around Tunneling FETs

IEEE Journal of the Electron Devices Society
A closed-form, analytical, and unified model for the surface potential from source to drain in nanowire (NW) gate-all-around (GAA) tunneling field effect transistors (TFETs) is proposed and validated.
Zhanhang Chen +7 more
doaj +1 more source

Nanosheet integration of induced tunnel field-effect transistor with lower cost and lower power

Discover Nano
Nanosheet transistors are poised to become the preferred choice for the next generation of smaller-sized devices in the future. To address the future demand for high-performance and low-power computing applications, this study proposes a nanosheet ...
Jyi-Tsong Lin, Chia-Yo Kuo
doaj +1 more source

Numerical Analysis of Current–Voltage Characteristics of LWIR nBn and p-on-n HgCdTe Photodetectors [PDF]

, 2013
K. Jóźwikowski, M. Kopytko
core +1 more source

Modeling trap dynamics in oxide-engineered heterostructure TFETs for breast cancer detection. [PDF]

Sci Rep
Ghosh R, Saha P.
europepmc +1 more source

Impact of drain and source engineering on dual metal InAs-GaSb VTFETs with high-K gate stack design. [PDF]