Results 91 to 100 of about 573 (171)

Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory

IEEE Journal of the Electron Devices Society
In this paper, we propose a low-power stack-level programming scheme for ultrahigh stack 3D NAND flash memory. As the number of word lines (WLs) increases beyond 300 layers, the increased pass voltage leads to excessive power consumption and reliability ...
Kyungmin Lee, Gunwook Yoon, Seung Jae Baik, Myounggon Kang   +3 more
doaj   +1 more source

A compact model for double-gate tunneling field-effect-transistors and its implications on circuit behaviors

, 2012
A compact model for tunneling field-effect-transistors (TFETs) is presented. The model includes a band-to-band tunneling (BTBT) current module and a terminal charge module.
Zhang, Lining, Lining Zhang, Chan, Mansun, He, Jin, Mansun Chan, Jin He   +5 more
core   +1 more source

An analytic model for gate-all-around silicon nanowire tunneling field effect transistors

, 2014
An analytical model of gate-all-around (GAA) silicon nanowire tunneling field effect transistors (NW-TFETs) is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling (BTBT) efficiency.
Zhao, Wei, Deng, Wan Ling, Du, Cai Xia, Liu, Ying, Ye, Yun, Chan, Mansun, He, Jin, Wang, Wen Ping, Wu, Wen   +8 more
core   +1 more source

Impact of calibrated band-tails on the subthreshold swing of pocketed TFETs

, 2018
© 2018 IEEE. The tunnel field-effect transistor (TFET) is one of the prime steep-slope device candidates to be employed in future ultra-low power logic applications [1], [2], and can achieve sub-60 mV/dec subthreshold swings (SS) using quantum ...
Bizindavyi, Jasper, Soree, Bart, Verhulst, Anne S., Groeseneken, Guido   +3 more
core   +1 more source

Line Tunneling Dominating Charge Transport in SiGe/Si Heterostructure TFETs

, 2016
This paper provides an experimental proof that both the ON-current ION and the subthreshold swing SS of Si(Ge)-based tunneling FETs (TFETs) drastically benefit from device architectures promoting line tunneling aligned with the gate electrical field.
Tiedemann, Andreas, Narimani, Keyvan, Schulte-Braucks, Christian, Glass, Stefan, Trellenkamp, Stefan, von den Driesch, Nils, Wirths, Stephan, Buca, Dan Mihai, Zhao, Qing-Tai, Mantl, Siegfried, Blaeser, Sebastian   +10 more
core   +1 more source

Ge/Si Core/Shell Nanowire Structures for Tunneling Devices

, 2010
In this work, the concept of band-to-band tunneling (BTBT) devices is explored and the benefits of Ge/Si core/shell nanowire heterostructures (NWHs) as a material/geometry-related choice are discussed, namely increased performance accessible by 1D ...
Joshua T. Smith, Yanjie Zhao, Ali Razavieh, Joerg Appenzeller, Chen Yang   +4 more
core   +1 more source

Effects of Local Electric Field and Effective Tunnel Mass on the Simulation of Band-to-Band Tunnel Diode Model

, 2005
We propose a numerical band-to-band tunneling model that is suitable for forward-biased silicon tunnel diode simulation. In this model, the tunneling attenuation factor, which depends on the local electric field and effective tunnel mass, determines the ...
Kim, Kyung Rok, Dutton, RW
core  

Low voltage SRAM design using tunneling regime of CNTFET

, 2014
This paper presents low-voltage techniques for static random access memory (SRAM) bit-cell design using the ambipolar characteristics of Carbon Nanotube field effect transistor (CNTFET).
Lining Zhang, Zhang, Lining, Khawar Sarfraz, Sarfraz, Khawar, Chan, Mansun, Mansun Chan, Zubair Ahmed, Ahmed, Zubair   +7 more
core   +1 more source

Nanosheet integration of induced tunnel field-effect transistor with lower cost and lower power

Discover Nano
Nanosheet transistors are poised to become the preferred choice for the next generation of smaller-sized devices in the future. To address the future demand for high-performance and low-power computing applications, this study proposes a nanosheet ...
Jyi-Tsong Lin, Chia-Yo Kuo
doaj   +1 more source

Surface-Potential-Based Drain Current Model of Gate-All-Around Tunneling FETs

IEEE Journal of the Electron Devices Society
A closed-form, analytical, and unified model for the surface potential from source to drain in nanowire (NW) gate-all-around (GAA) tunneling field effect transistors (TFETs) is proposed and validated.
Zhanhang Chen, Haoliang Shan, Ziyi Ding, Xia Wu, Xiaolin Cen, Xiaoyu Ma, Wanling Deng, Junkai Huang   +7 more
doaj   +1 more source