Results 81 to 90 of about 6,173 (209)
Single-charge devices with ultrasmall Nb/AlOx/Nb trilayer Josephson junctions
Josephson junction transistors and 50-junction arrays with linear junction dimensions from 200 nm down to 70 nm were fabricated from standard Nb/AlOx/Nb trilayers.
A. B. Zorin +4 more
core +1 more source
Microstructural Effects During Chemical Mechanical Planarization of Copper [PDF]
Novel die-stacking schema using through-wafer interconnects require vias to be filled with electroplated Cu, resulting in thick copper films, and requiring an aggressive first-step CMP.
Andersen, Patrick J. +3 more
core +2 more sources
Mimicking natural tubular structures, metal‐free conjugated hollow fibers are synthesized via one‐pot Chichibabin condensation. Pyridinic networks spontaneously self‐assemble into submicron hollow fibers and entangle into spongy monoliths—without templates, metals, or post‐processing.
Songah Jeong, Hyungwoo Kim
wiley +1 more source
Monolithic 3D Nanoelectrode Arrays on CMOS Circuitry for Scalable, High‐Resolution Neural Recording
A CMOS‐integrated in vitro electrophysiology platform with 26,400 3D nanoelectrodes enables high‐resolution extracellular recordings with enhanced spatial sensitivity. Wafer‐scale, low‐temperature post‐fabrication monolithic integration of nanoelectrodes on foundry‐made CMOS chips preserves circuit functionality and electrical performance.
Aziliz Lecomte +4 more
wiley +1 more source
Scratching by pad asperities in chemical mechanical polishing [PDF]
Thesis (S.B.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p.
Roberts, Michael P. (Michael Philip)
core
A DUV‐VCSEL strategy featuring the nanometer‐class control of the cavity length is proposed in the DUV optoelectronic framework based on GaN templates. After the sapphire removal, a self‐terminated etching technology is developed, whereby the cavity length can be accurately determined by epitaxy instead of the fabrication process. As such, a record low
Chen Ji +18 more
wiley +1 more source
Non-Uniformity of Wafer and Pad in CMP: Kinematic Aspects of View [PDF]
[[abstract]]In this paper, we analyze the non-uniformity of sliding distance on both wafer and polishing pad from kinematic point of view. Using the Fourier series expansion, we can show that in steady state the non-uniformity is determined by the ratio ...
[[alternative]]田豐, Tyan, Feng
core +1 more source
Production and characterization of microcapsules consisting of melamine-formaldehyde wall material
Semiconductor integrated circuits use ultra-flat substrates called wafers, in which minute irregularities are eliminated to the utmost limit. To produce such a flat substrate, a polishing technique called chemical mechanical polishing (CMP) is used.
Takumi Sayo +9 more
doaj +1 more source
Material Removal Characteristics of Abrasive-Free Cu Chemical-Mechanical Polishing (CMP) Using Electrolytic Ionization via Ni Electrodes. [PDF]
Lee H.
europepmc +1 more source
Polyamines have become important chemical components used in several integrated circuit manufacturing processes, such as etching, chemical mechanical polishing (CMP), and cleaning.
Ziwei Lin +5 more
doaj +1 more source

