Results 11 to 20 of about 441 (179)

Enhanced zero-phonon line emission from an ensemble of W centers in circular and bowtie Bragg grating cavities. [PDF]

Nanophotonics
Abstract Color centers in silicon have recently gained considerable attention as single‐photon sources and as spin qubit‐photon interfaces. However, one of the major bottlenecks to the application of silicon color centers is their low overall brightness due to a relatively slow emission rate and poor light extraction from silicon. Here, we increase the
Kizhake Veetil V, Song J, Namboodiri PN, Ebadollahi N, Chanana A, Katzenmeyer AM, Pederson C, Pomeroy JM, Chiles J, Shainline J, Srinivasan K, Davanco M, Pelton M.   +12 more
europepmc   +2 more sources

Cooperative Caching for Chip Multiprocessors [PDF]

33rd International Symposium on Computer Architecture (ISCA'06), 2006
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP's aggregate on-chip cache resources. Cooperative caching combines the strengths of private and shared cache organizations by forming an aggregate "shared" cache through cooperation among private caches.
Jichuan Chang, Gurindar S. Sohi
openaire   +1 more source

Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

International Journal of Reconfigurable Computing, 2012
This paper presents the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC) memory core. The memory core supports the flexibility of a heterogeneous FPGA-based runtime adaptive multiprocessor system ...
Diana Göhringer, Lukas Meder, Stephan Werner, Oliver Oey, Jürgen Becker, Michael Hübner   +5 more
doaj   +1 more source

Adaptive Dynamic Shortest Path Search Algorithm in Networks-on-Chip Based on Circulant Topologies

IEEE Access, 2021
A new pair routing algorithm for transmitting messages in multiprocessor systems and networks-on-chip based on circulant networks of arbitrary dimension is proposed.
Oleg G. Monakhov, Emilia A. Monakhova, Aleksandr Yu. Romanov, Andrej M. Sukhov, Evgenii V. Lezhnev   +4 more
doaj   +1 more source

Scaling and Packing on a Chip Multiprocessor [PDF]

2007 IEEE International Parallel and Distributed Processing Symposium, 2007
Power management is critical in server and high-performance computing environments as well as in mobile computing. Many mechanisms have been developed over recent years to support a wide a variety of power management techniques. In particular, general purpose microprocessors now support dynamically modifying the power-performance state through voltage ...
Vincent W. Freeh, Tyler K. Bletsch, Freeman L. Rawson III   +2 more
openaire   +1 more source

Energy Aware Parallel Scheduling Techniques for Network-on-Chip Based Systems

IEEE Access, 2021
Minimizing execution time, energy consumption, and network load through scheduling algorithms is challenging for multi-processor-on-chip (MPSoC) based network-on-chip (NoC) systems. MPSoC based systems are prevalent in high performance computing systems.
Bichi Bashir Yusuf, Tahir Maqsood, Faisal Rehman, Sajjad A. Madani   +3 more
doaj   +1 more source

Proximity coherence for chip multiprocessors [PDF]

Proceedings of the 19th international conference on Parallel architectures and compilation techniques, 2010
Many-core architectures provide an efficient way of harnessing the increasing numbers of transistors available in modern fabrication processes. While they are similar to multi-node systems, they exhibit different communication latency and storage characteristics, providing new design opportunities that were previously not feasible.
Nick Barrow-Williams, Christian Fensch, Simon W. Moore   +2 more
openaire   +2 more sources

Hardware Trojan Detection and Mitigation in NoC using Key authentication and Obfuscation Techniques

Emitter: International Journal of Engineering Technology, 2022
Today's Multiprocessor System-on-Chip (MPSoC) contains many cores and integrated circuits. Due to the current requirements of communication, we make use of Network-on-Chip (NoC) to obtain high throughput and low latency.
Thejaswini P, Vivekananda G, Anu H, Priya R, Krishna Prasad B S, Nischay M   +5 more
doaj   +1 more source

Realtime multiprocessor for mobile ad hoc networks [PDF]

Advances in Radio Science, 2008
This paper introduces a real-time Multiprocessor System-On-Chip (MPSoC) for low power wireless applications. The multiprocessor is based on eight 32bit RISC processors that are connected via an Network-On-Chip (NoC). The NoC follows a novel approach with
T. Jungeblut, M. Grünewald, M. Porrmann, U. Rückert   +3 more
doaj  

On Bipartite Circulant Graph Decompositions Based on Cartesian and Tensor Products with Novel Topologies and Deadlock-Free Routing

Algorithms, 2022
Recent developments in commutative algebra, linear algebra, and graph theory allow us to approach various issues in several fields. Circulant graphs now have a wider range of practical uses, including as the foundation for optical networks, discrete ...
Ahmed El-Mesady, Aleksandr Y. Romanov, Aleksandr A. Amerikanov, Alexander D. Ivannikov   +3 more
doaj   +1 more source