Results 21 to 30 of about 441 (179)
Networks on Chips: Structure and Design Methodologies
Journal of Electrical and Computer Engineering, 2012 The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip ...
Wen-Chung Tsai +3 more
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Technologies, 2022 Some complex digital circuits must host various operating systems in a single electronic platform to make real-time and not-real-time tasks compatible or assign different priorities to current applications.
Jaime Jiménez +4 more
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MRBS: An Area-Efficient Multicast Router for Network-on-Chip Using Buffer Sharing
IEEE Access, 2021 Network-on-chip (NoC) has become the mainstream fabric architecture for chip multiprocessor (CMP) design. Owing to the market-driven advancement of modern applications in CMP, multicast traffic is aggressively increasing to support barrier ...
Min Chae Yang +2 more
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Systems, 2017 Approaches for the design of fault tolerant Network-on-Chip (NoC) for use in System-on-Chip (SoC) reconfigurable technology using Field-Programmable Gate Array (FPGA) technology are challenging, especially in Multiprocessor System-on-Chip (MPSoC) design.
Hayat Daoud +4 more
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A HETEROGENEOUS MULTIPROCESSOR SYSTEM-ON-CHIP ARCHITECTURE INCORPORATING MEMORY ALLOCATION [PDF]
ICTACT Journal on Communication Technology, 2010 This paper describes the development of a Multiprocessor System-on-Chip (MPSoC) with a novel interconnect architecture incorporating memory allocation. It addresses the problem of mapping a process network with data dependent behavior and soft real time ...
T.Thillaikkarasi +2 more
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A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip
International Journal of Reconfigurable Computing, 2009 Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world.
Diana Göhringer +3 more
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Memory Map: A Multiprocessor Cache Simulator
Journal of Electrical and Computer Engineering, 2012 Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major
Shaily Mittal, Nitin
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Hardware Accelerators for Elliptic Curve Cryptography [PDF]
Advances in Radio Science, 2008 In this paper we explore different hardware accelerators for cryptography based on elliptic curves. Furthermore, we present a hierarchical multiprocessor system-on-chip (MPSoC) platform that can be used for fast integration and evaluation of novel ...
C. Puttmann +3 more
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Maskay, 2013 En el presente documento se presenta una breve caracterización de los medios de comunicación empleados en arquitecturas multiprocesadas. Esta caracterización tiene como objetivo principal el mostrar un nuevo modelo de comunicación basado en conmutación ...
Wilson Mauricio Chicaiza +1 more
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High‐Performance GPU Techniques for 2D Convolution Operators in Deep Neural Networks
Concurrency and Computation: Practice and Experience, Volume 38, Issue 14, July 2026.ABSTRACT This paper presents an optimized implementation of Winograd non‐fused convolution. Our optimizations include both application‐independent and Winograd‐specific software techniques, such as a specialized interface‐kernel data format (tile‐united CNHW layout) to enhance memory access efficiency; warp specialization and double‐buffered ...
Hui Wei +8 more
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