Results 31 to 40 of about 441 (179)

Advancing Software Development for a Multiprocessor System-on-Chip [PDF]

Journal of Systemics, Cybernetics and Informatics, 2007
A low-level language is the right tool to develop applications for some embedded systems. Notwithstanding, a high-level language provides a proper environment to develop the programming tools.
Stephen Bique
doaj  

Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems

International Journal of Reconfigurable Computing, 2011
The design space of FPGA-based processor systems is huge, because many parameters can be modified at design- and runtime to achieve an efficient system solution in terms of performance, power and energy consumption.
Diana Göhringer, Jonathan Obie, André L. S. Braga, Michael Hübner, Carlos H. Llanos, Jürgen Becker   +5 more
doaj   +1 more source

Rethinking Per‐Thread Computation for Machine Learning Design Exploration: A Work‐Efficient GPU Strategy for K‐Means and XGBoost

Concurrency and Computation: Practice and Experience, Volume 38, Issue 11, June 2026.
ABSTRACT This paper presents novel GPU implementation strategies that effectively exploit the available parallelism, based on the “more work per thread” approach, for three machine learning design exploration tasks: Multiple K‐means evaluation, dimensionality reduction through parallel K‐means encoding for XGBoost trees, and XGBoost tree pruning ...
Olavo Barros, Isabela Freitas, Pedro H. Pereira, Walter de B. Neto, Adrián Alcolea, María Villarroya‐Gaudó, Javier Resano, José Augusto M. Nacif, Ricardo Ferreira   +8 more
wiley   +1 more source

Memetic-based schedule synthesis for communication on time-triggered embedded systems

International Journal of Distributed Sensor Networks, 2017
Time-triggered systems play an important role in industrial embedded systems. The time-triggered network is deployed on the time-triggered network-on-chip implementation.
Heyuan Shi, Kun Tang, Chengbao Liu, Xiaoyu Song, Chao Hu, Jiaguang Sun   +5 more
doaj   +1 more source

Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors [PDF]

IEEE Transactions on Computers, 2008
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intra-chip and off-chip communication on the overall power budget.
Assaf Shacham, Keren Bergman, Luca P. Carloni   +2 more
openaire   +1 more source

MPI‐Based Approaches to Overlap Computation and I/O in Geophysical Simulations

Concurrency and Computation: Practice and Experience, Volume 38, Issue 7, April 2026.
ABSTRACT Geophysical simulations, such as wave propagation, are often constrained by I/O bottlenecks, where a significant portion of the execution time is spent writing data to disk. This process frequently leaves expensive computational resources, such as GPUs, idle, directly impacting both performance and energy consumption.
Rodrigo C. Machado, Arthur F. Lorenzon, Philippe O. A. Navaux   +2 more
wiley   +1 more source

Optimized Parallel Reduction for Regular and Irregular Segments on GPU

Concurrency and Computation: Practice and Experience, Volume 38, Issue 8, April 2026.
ABSTRACT Reduction is an operation that combines all the elements of a collection by applying a binary operation, such as sum, maximum, or minimum, to all the elements to obtain a single resulting value. This paper investigates implementation strategies for both segmented and non‐segmented reduction on GPUs.
Michel B. Cordeiro, Wagner M. Nunan Zola
wiley   +1 more source

DoS Attack Detection and Path Collision Localization in NoC-Based MPSoC Architectures

Journal of Low Power Electronics and Applications, 2019
Denial of Service (DoS) attacks are an increasing threat for Multiprocessor System-on-Chip (MPSoC) architectures. By exploiting the shared resources on the chip, an attacker is able to prevent completion or degrade the performance of a task.
Cesar Giovanni Chaves, Siavoosh Payandeh Azad, Thomas Hollstein, Johanna Sepúlveda   +3 more
doaj   +1 more source

Efficient Scheduling Algorithms for Multicore Cyclic Executives With Precedence and Exclusion Relations

Concurrency and Computation: Practice and Experience, Volume 38, Issue 5, March 2026.
ABSTRACT Cyclic executives (CEs) offer the advantage of ensuring complete determinism with minimal runtime overhead, often making them the preferred choice for safety‐critical real‐time systems. However, generating CEs for multicore processors while addressing task precedence and exclusion relations presents significant challenges.
Bruno Nogueira, Alfredo Lima, Eduardo Tavares, Rodrigo Paes, Francisco Airton Silva   +4 more
wiley   +1 more source

QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection

International Journal of Reconfigurable Computing, 2012
As electronic systems are pervading our lives, MPSoC (multiprocessor system-on-chip) security is becoming an important requirement. MPSoCs are able to support multiple applications on the same chip.
Johanna Sepulveda, Ricardo Pires, Guy Gogniat, Wang Jiang Chau, Marius Strum   +4 more
doaj   +1 more source