Results 41 to 50 of about 441 (179)
Research on the dynamic division and management of resources on multiprocessor system-on-chip
Dianzi Jishu Yingyong, 2018 To increase the scalability of cores, many methods are used, including Network on Chip(NoC) and cluster-based distributed management scheme. The application-based re-clustering algorithm has been delved deeply, while fixed-sized cluster is less developed,
Jia Minzheng, Fu Fangfa
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IEEE Transactions on Quantum Engineering, 2023 Electronic control systems used for quantum computing have become increasingly complex as multiple qubit technologies employ larger numbers of qubits with higher fidelity target.
Nafis Irtija +5 more
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Time‐ and Behaviour‐Preserving Execution of Determinate Supervisory Control
IET Cyber-Physical Systems: Theory &Applications, Volume 11, Issue 1, January/December 2026.The activity framework is a model‐based framework incorporating a model of activities with determinate timing and behaviour, and a strong mathematical foundation based on max‐plus algebra that allows efficient timing analysis and optimisation of CPS. Preserving the specified behaviour and the model‐predicted timing in an implementation is challenging ...
Alireza Mohamadkhani +3 more
wiley +1 more source
Multiprocessor Configuration of 8051 Microcontroller Chip
Journal of Engineering and Sustainable Development, 2011 This paper extends the parallel operation of the 8051 microcontroller chip and presents the use of multiple 8051s that are connected to a common loop in a multiprocessor configuration.
Ammar Ibrahim Majeed +3 more
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Safe Scheduling of Tasks in Temporal‐Domain for Multicore‐based IMA System
International Journal of Aerospace Engineering, Volume 2026, Issue 1, 2026.Multicore processors (MCPs) exhibit significant potential as airborne processors in Integrated Modular Avionics (IMA) systems. For IMA systems employing MCPs, a dual‐layer scheduling architecture is adopted to ensure task real‐time performance. However, existing scheduling designs based on ARINC 653 primarily focus on the spatial allocation of tasks ...
Changxiao Zhao, Yixuan Sun, Yuxiao Luo
wiley +1 more source
Operating System for Runtime Reconfigurable Multiprocessor Systems
International Journal of Reconfigurable Computing, 2011 Operating systems traditionally handle the task scheduling of one or more application instances on processor-like hardware architectures. RAMPSoC, a novel runtime adaptive multiprocessor System-on-Chip, exploits the dynamic reconfiguration on FPGAs to ...
Diana Göhringer +3 more
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Predictive coordination of multiple on-chip resources for chip multiprocessors [PDF]
Proceedings of the international conference on Supercomputing, 2011 Efficient on-chip resource management is crucial for Chip Multiprocessors (CMP) to achieve high resource utilization and enforce system-level performance objectives. Existing multiple resource management schemes either focus on intra-core resources or inter-core resources, missing the opportunity for exploiting the interaction between these two level ...
Jian Chen 0030, Lizy Kurian John
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Scaling Invariant Generation Using State Space Embeddings and GPU Streaming
Concurrency and Computation: Practice and Experience, Volume 37, Issue 25-26, 30 November 2025.ABSTRACT The formal verification of railway control systems can ensure the safety of complex scheme plans through techniques such as induction‐based model checking. While inductive verification performs well in complex settings, it often produces false positives due to its consideration of transitions from unreachable safe states to unsafe states ...
Ben Lloyd‐Roberts +4 more
wiley +1 more source
Leveraging SYCL for Heterogeneous cDTW Computation on CPU, GPU, and FPGA
Concurrency and Computation: Practice and Experience, Volume 37, Issue 15-17, 25 July 2025.ABSTRACT One of the most time‐consuming kernels of a recent epileptic seizure detection application is the computation of the constrained Dynamic Time Warping (cDTW) Distance Matrix. In this paper, we explore the design space of heterogeneous CPU, GPU, and FPGA implementations of this kernel using SYCL as a programming model. First, we optimize the CPU
Cristian Campos +3 more
wiley +1 more source
Journal of Computer Science and Technology, 2006 Chip-multiprocessor systems or CMPs have emerged as a high-perfomance organization for the increasing number of transistors available on a chip, and are projected to dominate the market of server and desktop computers.
Francisco J. Villa +2 more
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