Results 1 to 10 of about 13,469 (166)
Monolithic integration of p- and n-type doped 2D WSe2 for wafer-scale complementary logic circuits [PDF]
Atomically thin two-dimensional (2D) semiconductors are promising candidates for next-generation electronics, which could effectively suppress short-channel effects and consequently reduce static power consumption.
Yan Hu +32 more
doaj +2 more sources
A Three-Axis Magnetic Field Microsensor Fabricated Utilizing a CMOS Process
This study develops a three-axis magnetic field (MF) microsensor manufactured by a complementary metal oxide semiconductor (CMOS) process. The MF microsensor contains a ring emitter, four bases, and eight collectors.
Jian-Zhi Tseng +3 more
doaj +3 more sources
Generic logic block based on bias-gated 2D MoS2 transistors [PDF]
Integrating two-dimensional (2D) semiconductors and CMOS technology is a promising pathway for next-generation integrated circuits. However, the implementation of this strategy is hindered by the limited polarity modulation of 2D semiconductors and the ...
Xiaofu Wei +10 more
doaj +2 more sources
CMOS-Compatible Micro Photovoltaic Generator with Post-Processing Enhanced Optical Absorption [PDF]
This work reports the design and realization of a silicon-based micro photovoltaic generator (MPG) fabricated using a standard 0.18 μm complementary metal oxide semiconductor (CMOS) technology.
Hung-Wei Chen +2 more
doaj +2 more sources
A Tunable-Gain Transimpedance Amplifier for CMOS-MEMS Resonators Characterization
CMOS-MEMS resonators have become a promising solution thanks to their miniaturization and on-chip integration capabilities. However, using a CMOS technology to fabricate microelectromechanical system (MEMS) devices limits the electromechanical ...
Rafel Perelló-Roig +3 more
doaj +1 more source
Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits
The integrated circuit (IC) products fabricated in the scaled-down CMOS processes with higher clock rate and lower power supply voltage (VDD) are more sensitive to the transient/switching noises on the power lines with the parasitic inductance induced by
Yi-Chun Huang, Ming-Dou Ker
doaj +1 more source
In this study, we experimentally demonstrated concepts for realizing doping-free Tungsten Diselenide (WSe2) complementary metal-oxide-semiconductor (CMOS) inverter by developing alloys and compound metals used as source/drain (S/D) contacts.
Takamasa Kawanago +8 more
doaj +1 more source
Novel pure‐metal tri‐axis CMOS‐MEMS accelerometer design and implementation
This work proposed a pure‐metal, single‐proof‐mass structure fabricated by the standard 0.18 μm one‐poly‐silicon six‐metal (1P6M) CMOS process along with one in‐house post‐CMOS wet‐etching approach.
Jung‐Hung Wen, Weileum Fang
doaj +1 more source
Effects of COVID‐19 on a CMOS fabrication course: An integrated design experience [PDF]
AbstractIn the CMOS fabrication course described herein, the lecture component provides the theoretical background for semiconductor materials and integrated circuit fabrication processes. The laboratory component provides the hands‐on experience required to fabricate and electrically characterize CMOS circuits in a one‐semester format.
Seung‐Joon Paik, A. Bruno Frazier
openaire +2 more sources
We propose a CMOS image sensor with a dedicated low-power imaging mode and low-power integrated transmitter. The proposed CMOS image sensor selectively operates in dual mode: a high-quality mode with a 1.5 V supply voltage of readout circuits to achieve ...
Sang-Hoon Kim +4 more
doaj +1 more source

