Results 241 to 250 of about 36,961 (291)

Phase-domain all-digital phase-locked loop

IEEE Transactions on Circuits and Systems II: Express Briefs, 2005
A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator that deliberately avoids any analog tuning controls. When implemented in a digital deep-submicrometer CMOS process, the proposed architecture appears more advantageous over conventional charge-pump ...
R.B. Staszewski, P.T. Balsara
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Synthesizable Digital Phase Locked Loop Implementation

Advanced Materials Research, 2013
Phase locked loop (PLL) is a very common circuit in the most of the electrical devices. The systems where needed clock or data recovery or frequency synthesis, PLL is the most cost effective and efficient choice that from cellular phone in our hands to the computers, televisions, radios and a different controller, PLL is everywhere.
Rajib Imran, Monirul Islam, Abdullah Al Kafi   +2 more
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Digital phase-locked loops

2018 IEEE Custom Integrated Circuits Conference (CICC), 2018
▪ Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control ▪ In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution ▪ Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power ...
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New dual digital phase‐locked loop

Electronics and Communications in Japan (Part I: Communications), 1986
AbstractIn the phase‐locked loop (PLL), the following mehods are used to eliminate the steady‐state phase error produced by the input signal with frequency off‐set: (1) the perfect integrator is used as the loop filter, realizing the perfect second‐order PLL; (2) the dual phase‐locked loop (DuLL) is constructed by combining two first‐order PLL's ...
Shoichiro Yamasaki, Masao Nakagawa, Toshio Tsunogae   +2 more
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Quasi-Optimum Digital Phase-Locked Loops

IEEE Transactions on Communications, 1973
Quasi-optimum digital phase-locked loops (DPLL) are derived utilizing nonlinear estimation theory. Nonlinear approximations are employed to yield realizable loop structures. Baseband equivalent loop gains are derived, which, under high signal-to-noise ratio conditions may be calculated off line.
D. Polk, S. Gupta
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CMOS High-Resolution All-Digital Phase-Locked Loop

2003 46th Midwest Symposium on Circuits and Systems, 2006
The core of an all-digital phase locked-loop (ADPLL) is composed of a high resolution digital controlled oscillator (DCO) circuit operating in a wide frequency range, a phase-frequency detector (PFD) and an up/down binary counter. The ADPLL can be reused in many system-on-chip (SoC) applications by a proper setting of the DCO and the PFD.
E. Mokhtari, M. Sawan
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Advanced digital phase-locked loops

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Analog PLLs do not scale down as process and are not amenable to noise-cancellation and other calibration algorithms; Digital PLLs exploit CMOS scaling and allow for simple, accurate implementation of digiphase and two-point modulation; Typically, DPLLs require TDCs with tight resolution to achieve low phase noise and fractional-spur level, which ...
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Quantization Effects in All-Digital Phase-Locked Loops

IEEE Transactions on Circuits and Systems II: Express Briefs, 2007
This brief analyzes the impact of the quantization noise sources in all-digital phase-locked loops (ADPLLs), recently employed as frequency synthesizers. In general, the in-band phase noise is not only caused by the phase quantization of the time-to-digital converter, but also by the frequency quantization of the digitally controlled oscillator (DCO ...
P. Madoglio, M. Zanuso, LEVANTINO, SALVATORE, SAMORI, CARLO, LACAITA, ANDREA LEONARDO   +4 more
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Phase-jitter dynamics of digital phase-locked loops

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 1999
Recent work on the subject of digital phase-locked loops (DPLL's) has examined the unwanted phase jitter that occurs in such systems due to frequency quantization in a number-controlled oscillator. In this paper, we show that the theory of nonlinear dynamics can provide an analytical explanation of this phase jitter, along with other features of the ...
A. Teplinsky, O. Feely, A. Rogers
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First-Order Digital Phase Lock Loop with Continuous Locking

2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks, 2013
A zero-crossing digital phase locked loop (ZCDPLL) system with dual gain selection technique for fast acquisition, reliable locking and improved phase noise and jitter performance is proposed. The system is designed and simulated based on adaptive loop gain techniques.
Saleh R. Al-Araji, Kahtan A. Mezher, Qassim Nasir   +2 more
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