Results 251 to 260 of about 36,961 (291)
Some of the next articles are maybe not open access.
A high lock-in speed digital phase-locked loop
IEEE Transactions on Communications, 1991A digital phase-locked loop (DPLL) consisting of a modified 9-gate phase detector, a frequency multiplier, and a loop filter is described. All the components are implemented in digital hardware. The Z-transform is employed to deduce the system function, and some simple properties of the DPLL are inferred by examining the mathematical model.
null Shi Hao, null Yan Puqiang
openaire +1 more source
A survey of digital phase-locked loops
Proceedings of the IEEE, 1981The purpose of this paper is to present a systematic survey of the theoretical/experimental work accomplished in the area of digital phase-locked loops (DPLL's) during the period of 1960 to 1980. The DPLL represents the heart of the Building blocks required in the implementation of coherent (all digital) communications and tracking receivers.
W.C. Lindsey, null Chak Ming Chie
openaire +1 more source
Fractional-Order Digital Phase-Locked Loop
2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007A fractional-order digital phase-locked loop (FODPLL) is proposed. The FODPLL model is developed by approximating a fractional-order digital controlled-oscillator (FODCO) with a finite dimensional discrete transfer function. The design of FODPLLs model is simplified where one only needs to design a FODCO.
openaire +1 more source
A Novel Flash Fast-Locking Digital Phase-Locked Loop
2009 Sixth International Conference on Information Technology: New Generations, 2009A FLASH digital phase-locked loop (DPLL) is designed using 0.18μm CMOS process and a 3.3V power supply. It operates in the frequency range 200MHz – 2GHz. The DPLL operation includes two stages: (1) a novel coarse-tuning stage based on a flash algorithm similar to the algorithm employed in flash A/D converters, and (2) a fine-tuning stage similar to ...
Mahmoud Fawzy Wagdy +1 more
openaire +1 more source
A Digital BIST for Phase-Locked Loops
2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008This paper presents a conceptual implementation of a jitter measurement circuit with several BIST (built-in self test) features for embedded phase-locked loops. We demonstrate a fully functional jitter measurement circuit capable of detecting cycle-to-cycle jitter.
Kevin Sliech, Martin Margala
openaire +1 more source
Digital phase-locked loop with jitter bounded
IEEE Transactions on Circuits and Systems, 1989A design of an all-digital phase-locked loop (DPLL) with direct frequency synthesis is proposed for generating signals that satisfy preimposed requirements on jitter over any given range of frequencies. Control of the jitter is obtained by means of a frequency-phase window comparator which compares the bit overflow/underflow of the direct synthesis ...
S.M. Walters, T. Troudet
openaire +1 more source
Unbiased Finite-Memory Digital Phase-Locked Loop
IEEE Transactions on Circuits and Systems II: Express Briefs, 2016Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the ...
You, S. +4 more
openaire +2 more sources
All Digital Phase-Locked Loops
1998In this chapter, we are going to extend our survey to loops that have do not have analog prototypes. Lindsey and Chie [1] performed a 1981 survey of digital PLLs that is recommended to the reader desiring additional architectures.
openaire +1 more source
A New DSP Digital Phase Locked Loop
IETE Journal of Research, 1993A new type of digital signal processing type digital phase locked loop is presented. It consists of a second order DPLL and first order DPLL both of which possess an additional automatic-frequency-...
B N Biswas +4 more
openaire +1 more source