Results 21 to 30 of about 7,307,662 (147)
MicromachinesThis paper proposes a cross-scale simulation approach for evaluating the steady-state electrothermal performance of power MOSFETs at the device–package–heatsink–board (DPHB) level.
Yuxuan Dai +9 more
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Sensitivity Study of Polysilicon Nanowire Based on Scattering and Quantum Mechanics Models
MATEC Web of Conferences, 2018 In this paper, we report nanowire drain saturation current sensitivity property to measure femtomol level change in drain current due to different proteins i.e.
Aanand +5 more
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Correlated Time-0 and Hot-Carrier Stress Induced FinFET Parameter Variabilities: Modeling Approach
Micromachines, 2020 We identify correlation between the drain currents in pristine n-channel FinFET transistors and changes in time-0 currents induced by hot-carrier stress.
Alexander Makarov +7 more
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Channel Engineering for Nanotransistors in a Semiempirical Quantum Transport Model
Mathematics, 2017 One major concern of channel engineering in nanotransistors is the coupling of the conduction channel to the source/drain contacts. In a number of previous publications, we have developed a semiempirical quantum model in quantitative agreement with three
Ulrich Wulf +5 more
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Eight Questions about Brain Drain [PDF]
High-skilled emigration is an emotive issue that in popular discourse is often referred to as brain drain, conjuring images of extremely negative impacts on developing countries. Recent discussions of brain gain, diaspora effects, and other advantages of
John Gibson, David McKenzie
core +4 more sources
Simulation Study of the Double-Gate Tunnel Field-Effect Transistor with Step Channel Thickness
Nanoscale Research Letters, 2020 Double-gate tunnel field-effect transistor (DG TFET) is expected to extend the limitations of leakage current and subthreshold slope. However, it also suffers from the ambipolar behavior with the symmetrical source/drain architecture.
Maolin Zhang +4 more
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Advanced Electronic Materials, 2023 Low saturation voltages and extremely high intrinsic gain can be achieved in contact‐controlled thin‐film transistors (TFTs) with staggered device architecture, enabled by the energy barrier introduced at the source contact.
Eva Bestelink +4 more
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Magnetically-coupled Current Sensor Using An Integrated Coil And A Cmos Split-drain Transistor
Eletrônica de Potência, 2006 An integrated current sensing circuit intended for Smart-Power and embedded applications featuring galvanic isolation is implemented. It is based on magnetic detection using the CMOS compatible Split- Drain transistor (MAGFET) that provides a very ...
Fernando C. Castaldo +1 more
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Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET
Micromachines, 2023 In this paper, we propose and investigate an electrically doped (ED) PNPN tunnel field effect transistor (FET), in which the drain side tunneling barrier width is effectively controlled to obtain a suppressed ambipolar current.
Chan Shan +4 more
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AIP Advances, 2023 Vertical thin-film transistors (V-TFTs) with an InSnO-stabilized ZnO channel were fabricated. The vertical architecture enables devices with submicron channel lengths (≤500 nm) to afford delivering drain current greatly exceeding that of conventional ...
Xue-Mei Yin +4 more
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