DRAM-3 modulates autophagy and promotes cell survival in the absence of glucose [PDF]
Macroautophagy is a membrane-trafficking process that delivers cytoplasmic constituents to lysosomes for degradation. The process operates under basal conditions as a mechanism to turnover damaged or misfolded proteins and organelles. As a result, it has
A Kuma +47 more
exaly +4 more sources
Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems [PDF]
Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today’s DRAM technology scaling challenges requires new solutions driven by
Minesh Patel +6 more
doaj +2 more sources
Novel three-dimensional stacked capacitorless DRAM architecture using partially etched nanosheets for high-density memory applications [PDF]
This study presents a novel three-dimensional stacked capacitorless dynamic random access memory (1T-DRAM) architecture, designed using a partially etched nanosheet (PE NS) to overcome the scaling limitations of traditional DRAM designs.
Min Seok Kim +9 more
doaj +2 more sources
Design of a gate-all-around arch-shaped tunnel-field-effect-transistor-based capacitorless DRAM [PDF]
In this study, we designed and analyzed a single-transistor dynamic random-access memory (1 T-DRAM) based on an arch-shaped gate-all-around tunnel field-effect transistor (GAA ARCH-TFET), featuring an Si/SiGe heterostructure, for high-density memory ...
Seung Ji Bae +9 more
doaj +2 more sources
Performance Analysis Of SRAM and Dram in Low Power Application [PDF]
All electronic systems must function quickly in the current environment, and 80 percent of electronic chips have memory components. SRAM (Static Random Access Memory) has thus become a major key component in many VLSI Chips in order to reduce the size of
Yuvaraj S. +5 more
doaj +1 more source
An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process
As the technology node of the dynamic random-access memory (DRAM) continues to decrease below the 10-nm-class, bit-cell failures due to the external environments have increased.
Jaewon Park +5 more
doaj +1 more source
DCA: A DRAM-cache-Aware DRAM Controller [PDF]
3D-stacking technology has enabled the option of embedding a large DRAM cache onto the processor. Since the DRAM cache can be orders of magnitude larger than a conventional SRAM cache, the size of its cache tags can also be large. Recent works have proposed storing these tags in the stacked DRAM array itself. However, this increases the complexity of a
Cheng-Chieh Huang +2 more
openaire +2 more sources
Performance evaluation of SRAM design using different field effect transistors [PDF]
SRAM (Static Random Access Memory) is one of the type of memory which holds the data bit without periodic refreshment. Compared with DRAM (Dynamic Random Access Memory) which requires periodic refreshment of data bit stored in it.
C. Venkataiah +5 more
doaj +1 more source
CYBER SECURITY IN INDUSTRIAL CONTROL SYSTEMS (ICS): A SURVEY OF ROWHAMMER VULNERABILITY [PDF]
Increasing dependence on Information and Communication Technologies (ICT) and especially on the Internet in Industrial Control Systems (ICS) has made these systems the primary target of cyber-attacks.
Hakan AYDIN , Ahmet SERTBAŞ
doaj +1 more source
DRAM Retention Behavior with Accelerated Aging in Commercial Chips
The cells in dynamic random access memory (DRAM) degrade over time as a result of aging, leading to poor performance and potential security vulnerabilities.
Md Kawser Bepary +2 more
doaj +1 more source

