Results 11 to 20 of about 97,626 (219)
Enabling Variability-Aware Design-Technology Co-Optimization for Advanced Memory Technologies
Journal of Microelectronic Manufacturing, 2020 This paper presents a TCAD-based methodology to enable Design-Technology Co-Optimization (DTCO) of advanced semiconductor memories. After reviewing the DTCO approach to semiconductor devices scaling, we introduce a multi-stage simulation flow to study ...
Salvatore M. Amoroso +9 more
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Serum starvation induces DRAM expression in liver cancer cells via histone modifications within its promoter locus. [PDF]
PLoS ONE, 2012 DRAM is a lysosomal membrane protein and is critical for p53-mediated autophagy and apoptosis. DRAM has a potential tumor-suppressive function and is downregulated in many human cancers.
Peihua Ni +8 more
doaj +1 more source
An Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Current Distribution
IEEE Journal of the Electron Devices Society, 2018 This paper is the first to propose an innovative method for measuring variations in dynamic random access memory (DRAM) cell transistors. Structural dispersion induces an extremely high cell leakage current, which determines aspects of DRAM performance ...
Min Hee Cho +7 more
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IEEE Access, 2023 Modern DRAM devices’ performance and energy efficiency are significantly improved when the row-buffer locality is exploited properly. In multi-core architectures, however, the DRAM-based main memory banks used by the processing units, called cores,
Tareq A. Alawneh +3 more
doaj +1 more source
Interposing Flash between Disk and DRAM to Save Energy for Streaming Workloads [PDF]
, 2007 In computer systems, the storage hierarchy, composed of a disk drive and a DRAM, is responsible for a large portion of the total energy consumed. This work studies the energy merit of interposing flash memory as a streaming buffer between the disk drive ...
Hartel, P.H. +3 more
core +6 more sources
网络与信息安全学报, 2018 The related technologies and defense methods of the current Row Hammer vulnerabilities were analyzed and summarized, and the security problems and possible precautions were pointed out.
WANG Wenwei, LIU Peishun
doaj +1 more source
Sensors, 2021 With technology scaling, maintaining the reliability of dynamic random-access memory (DRAM) has become more challenging. Therefore, on-die error correction codes have been introduced to accommodate reliability issues in DDR5.
Duy-Thanh Nguyen +3 more
doaj +1 more source
Emulating and evaluating hybrid memory for managed languages on NUMA hardware [PDF]
, 2019 Non-volatile memory (NVM) has the potential to become a mainstream memory technology and challenge DRAM. Researchers evaluating the speed, endurance, and abstractions of hybrid memories with DRAM and NVM typically use simulation, making it easy to ...
Akram, Shoaib +3 more
core +1 more source
Inverted bit‐line sense amplifier with offset‐cancellation capability
Electronics Letters, 2016 An inverted bit‐line sense amplifier (BLSA) equipped with offset compensation capability for low‐power DRAM applications is proposed. The sequential operation of the inverted BLSA allows us to eliminate the edge dummy array in an open bit‐line structure ...
J. Park +3 more
doaj +1 more source
ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM
IEEE Access, 2021 In sub-20 nm technologies, DRAM cells suffer from poor retention time. With the technology scaling, this problem tends to be worse, significantly increasing refresh power of DRAM.
Duy-Thanh Nguyen +4 more
doaj +1 more source